PCF8577CT/3,112 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCF8577CT/3,112 Datasheet PDF : 33 Pages
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NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
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Fig 8. System configuration
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8.1.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is not limited. Each byte is followed by one acknowledge bit. The
acknowledge bit is a HIGH level put on the I2C-bus by the transmitter whereas the master
generates an extra acknowledge related clock pulse. A slave receiver which is addressed
must generate an acknowledge after the reception of each byte. Also a master must
generate an acknowledge after the reception of each byte that has been clocked out of
the slave transmitter. The device that acknowledges has to pull down the SDA line during
the acknowledge clock pulse, set-up and hold times must be taken into account. A master
receiver must signal an end of data to the transmitter by not generating an acknowledge
on the last byte that has been clocked out of the slave. In this event, the transmitter must
leave the data line HIGH to enable the master to generate a STOP condition.
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Fig 9. Acknowledgement of the I2C-bus
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8.2 Slave address
The PCF8577C slave address is shown in Table 7.
Table 7. I2C slave address byte
Slave address
R/W
Bit
7
6
5
4
3
2
1
0
MSB
LSB
0
1
1
1
0
1
0
0
Before any data is transmitted on the I2C-bus, the device which should respond is
addressed first. The addressing is always done with the first byte transmitted after the
start procedure.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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