PCK2000M View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
PCK2000M Datasheet PDF : 12 Pages
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Philips Semiconductors
CK97 (66/100MHz) Mobile System Clock Generator
Product specification
PCK2000M
SELECT FUNCTIONS
SEL100/66
SEL0
0
0
0
1
1
0
1
1
NOTES:
1. Internal decode logic for all two select inputs implemented.
FUNCTION
TRI-State
Active 66MHz
Test mode
Active 100MHz
NOTES
1
1
FUNCTION
DESCRIPTION
Tri-State
Test mode
CPU
Hi-Z
TCLK/2
OUTPUTS
PCI, PCI_F
Hi-Z
TCLK/6
REF
Hi-Z
TCLK
FUNCTION TABLE
SEL 100/66
0
1
CPU/PCI RATIO
2
3
CPUCLK (0–1)
(MHz)
66.66
100
CPICLK (1–5)
PCICLK_F
(MHz)
33.33
33.33
REF
(MHz)
14.318
14.318
CLOCK ENABLE CONFIGURATION
CPUSTOP PCISTOP
PWRDWN
CPUCLK
X
X
0
LOW
0
0
1
LOW
0
1
1
LOW
1
0
1
100/66MHz
1
1
1
100/66MHz
PCICLK
LOW
LOW
33MHz
LOW
33MHz
PCICLK_F
LOW
33MHz
33MHz
33MHz
33MHz
OTHER
CLOCKS
Stopped
Running
Running
Running
Running
PLL
OFF
Running
Running
Running
Running
OSCILLATOR
OFF
Running
Running
Running
Running
POWER MANAGEMENT REQUIREMENTS
SIGNAL
SIGNAL STATE
LATENCY
NO. OF RISING EDGES OF FREE RUNNING
PCICLK
CPUSTOP
PCISTOP
PWRDWN
0 (DISABLED)
1 (ENABLED)
0 (DISABLED)
1 (ENABLED)
1 (NORMAL OPERATION)
0 (POWER DOWN)
1
1
1
1
3ms
2 MAX
NOTES:
1. Clock ON/OFF latency is defined as the number of rising edges of free running PCICLKs between the clock disable goes HIGH/LOW to the
first valid clock that comes out of the device.
2. Power up latency is when PWRDWN goes inactive (HIGH) to when the first valid clocks are driven from the device.
1998 Sep 29
4
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