ICS1889 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
Manufacturer
ICS1889 Datasheet PDF : 35 Pages
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ICS1889
4B/5B Encoder/Decoder
The ICS1889 uses a 4B5B coding scheme. This maps a 4-bit
nibble to a 5-bit code group called a symbol. Five bits allow
32 possible symbols, 16 are used for data encoding, 6 are used
for control and 10 are not used and are invalid. The control
symbols used are JK as the SSD, TR as the ESD, I as
the IDLE symbol and H to signal an error. All other
symbols are invalid and, if detected, will set the receive error
bit in the status register, and cause the RXER signal to be
asserted (see Table 1 below).
When transmitting, nibbles from the MII are converted to a 5-
bit code groups. During transmission, the first 16 nibbles
obtained from the MII are the MAC frame preamble.
The ICS1889 replaces the first two nibbles with the start-of-
stream delimiter (the JK symbol pair). Following the last
nibble, the ICS1889 adds the end-of-stream delimiter (the
TR symbol pair).
When receiving, 5-bit code groups are converted to nibbles
and presented to the MII. If the ICS1889 detects one or more
invalid symbols, it sets the Invalid Symbol bit (17:7) in the
QuickPoll Status Register. When receiving a frame, the first
two 5-bit code groups received are the start-of-stream
delimiter (the JK symbol pair), the ICS1889 strips them
and substitutes two nibbles of the normal preamble pattern.
The last two 5-bit code groups are the end-of-stream delimiter
(the TR symbol pair), these are stripped from the nibbles
presented to the MAC.
Symbol
0
1
2
3
4
5
6
7
Meaning
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Table 1: 4B5B Encoding
4B Code
3210
0000
0001
0010
0011
0100
0101
0110
0111
5B Code
43210
11110
01001
10100
10101
01010
01011
01110
01111
Symbol
8
9
A
B
C
D
E
F
Meaning
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
4B Code
3210
1000
1001
1010
1011
1100
1101
1110
1111
5B Code
43210
10010
10011
10110
10111
11010
11011
11100
11101
I
Idle
Undefined 1 1 1 1 1
V
Invalid
Undefined 0 0 0 1 0
J
SSD
0101 11000
V
Invalid
Undefined 0 0 0 1 1
K
SSD
0101 10001
V
Invalid
Undefined 0 0 1 0 1
T
ESD
Undefined 0 1 1 0 1
V
Invalid
Undefined 0 0 1 1 0
R
ESD
Undefined 0 0 1 1 1
V
Invalid
Undefined 0 1 0 0 0
H
Error
Undefined 0 0 1 0 0
V
Invalid
Undefined 0 1 1 0 0
V
Invalid
Undefined 0 0 0 0 0
V
Invalid
Undefined 1 0 0 0 0
V
Invalid
Undefined 0 0 0 0 1
V
Invalid
Undefined 1 1 0 0 1
Invalid Error Code Test TXER asserted
I
Idle
1111 11111
V
Invalid
0010
J
SSD
1110 11000
V
Invalid
0011
K
SSD
1011 10001
V
Invalid
0101
T
ESD
1001 01101
V
Invalid
0110
R
ESD
0111 00111
V
Invalid
1000
H
Error
0100 00100
V
Invalid
1010
V
Invalid
0000 00000
V
Invalid
1100
V
Invalid
0001 00001
V
Invalid
1101
1. The IDLE symbol is sent continuously between frames.
2. J and K are the SSD and are always sent in pairs.
3. K always follows J.
4. T and R are the ESD and are always sent in pairs.
5. R always follows T.
6. A HALT symbol is used to signal an error condition.
00010
00011
00101
00110
01000
01100
10000
11001
5
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