DM93L38N View Datasheet(PDF) - Fairchild Semiconductor
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DM93L38N Datasheet PDF : 6 Pages
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Functional Description
The DM93L38 8-bit multiple port register can be consid-
ered a 1-bit slice of eight high speed working registers.
Data can be written into any one and read from any two of
the eight locations simultaneously. Master/slave operation
eliminates all race problems associated with simultaneous
read/write activity from the same location. When the clock
input (CP) is LOW data applied to the data input line (DA)
enters the selected master. This selection is accomplished
by coding the three write input select lines (A0–A2) appro-
priately. Data is stored synchronously with the rising edge
of the clock pulse.
The information for each of the two slaved (output) latches
is selected by two sets of read address inputs (B0–B2 and
C0–C2). The information enters the slave while the clock is
HIGH and is stored while the clock is LOW. If Slave Enable
is LOW (SLE), the slave latches are continuously enabled.
The signals are available on the output pins (ZB and ZC).
The input bit selection and the two output bit selections can
be accomplished independently or simultaneously. The
data flows into the device, is demultiplexed according to
the state of the write address lines and is clocked into the
selected latch. The eight latches function as masters and
store the input data. The two output latches are slaves and
hold the data during the read operation. The state of each
slave is determined by the state of the master selected by
its associated set of read address inputs.
The method of parallel expansion is shown in Figure 1.
One DM93L38 is needed for each bit of the required word
length. The read and write input lines should be connected
in common on all of the devices. This register configuration
provides two words of n-bits each at one time, where n
devices are connected in parallel.
FIGURE 1. Parallel Expansion
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