PEB20324 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

PEB20324

Multichannel Network Interface Controller for HDLC + Extensions MUNICH128X

Infineon Technologies 

PEB 20324

PEF 20324

Introduction

1.4

Differences to the MUNICH32

• 128-channel capability

• Symmetrical Rx and Tx Buffer Descriptor formats for faster switching

• Improved Tx idle channel polling process for significantly reducing bus occupancy of

idle Tx channels

• Dedicated 1024 byte Tx Buffer

• Dedicated 1024 byte Rx Buffer

• Burst capability also on transmit and receive data sections (8 DWORDs)

• Additional PCM modes supported: 3.088 MBit/s, 6.176 MBit/s, 8.192 MBit/s

• 32 Bit / 33 MHz PCI 2.1 master/slave interface;

this interface can be configured in De-mux mode

• Separate Rx and Tx Status Queues in host memory

(the MUNICH128X provides one set for each of the four HDLC Controllers)

• Slave access to on-chip registers

• Time Slot-shift capability:

– Programmable from -4 clock edges to +3 clock edges

relative to the synchronization pulse

– Programmable to sample Tx and/or Rx data at either falling or rising edge of clock

• Software initiated action request (via the Command Register)

• Tx End-of-Packet transmitted-on-wire interrupt capability for each channel

• Tx packet size increased to 64 Kbytes (HDLC mode)

• Rx packet size 8 Kbyte limit interrupt disable

• Tx data TRISTATETM control line

• Synchronized data transfer in TMA mode

for complete transparency when using fractional T1/PRI

• Little/Big Endian data formats

Hardware Reference Manual

14

04.99

Share Link: