PEEL16CV8J-25 View Datasheet(PDF) - Anachip Corporation

Part Name

Description

Manufacturer

PEEL16CV8J-25

CMOS Programmable Electrically Erasable Logic Device

Anachip Corporation 

Complex Mode

In Complex mode, seven product terms feed the OR array which can

generate a purely combinatorial function for the output pin. The pro-

grammable output polarity selector provides active-high or active-low

logic, eliminating the need for external inverters. The output buffer is

controlled by the eighth product term, allowing the macrocell to be con-

figured for input, output, or bidirectional functions. Feedback into the

array for input or bidirectional functions is available on all pins except 12

and 19. Figure 4 shows the possible complex mode macrocell configura-

tions.

1 Registered Mode

Active Low Registered Output

OE PIN

CLK PIN

DQ

Q

2 Registered Mode

Active High Registered Output

OE PIN

CLK PIN

DQ

Q

3 Registered Mode

Active Low Combinatorial Output

PRODUCT TERM

4 Registered Mode

Active High Combinatorial Output

PRODUCT TERM

1 Complex Mode

Active Low Output

PRODUCT TERM

2 Complex Mode

Active High Output

PRODUCT TERM

Figure 5 - Macrocell Configurations for the Registered Mode of the

PEELTM 16CV8 (see Figure 8 for logic Array)

Figure 4 - Macrocell Configurations for the Complex Mode of the

PEELTM 16CV8 (see Figure 7 for Logic Array)

Registered Mode

Registered mode provides eight product terms to the OR array for regis-

tered functions. The programmable output polarity selector provides

active-high or active-low logic, eliminating the need for external invert-

ers. (Note, however, that if register is selected, the PEELTM 16CV8 reg-

gisters power-up reset and so before the first clock arrives the output at

the pin will be low if the user has selected active-high logic and high if the

user has selected active-low logic. If combinatorial is selected, the output

will be a function of the logic.) For registered functions, the output buffer

enable is controlled directly from the /OE control pin. Feedback into the

array comes from the macrocell register. In Registered mode, input pins

1 and 11 are permanently allocated as CLK and /OE, respec- tively. Figure

8 shows the logic array of the PEELTM 16CV8 configured in Registered

mode.

Design Security

The PEELTM 16CV8 provides a special EEPROM security bit that pre-

vents unauthorized reading or copying of designs programmed into the

device. The security bit is set by the PLD programmer, either at the con-

clusion of the programming cycle or as a separate step, after the device

has been programmed. Once the security bit has been set it is impossi-

ble to verify (read) or program the PEELTM until the entire device has first

been erased with the bulk-erase function.

Signature Word

The signature word feature allows a 64-bit code to be programmed into

the PEELTM 16CV8. The code cannot be read back after the security bit

has been set. The signature word can be used to identify the pattern

programmed into the device or to record the design revision, etc.

Registered mode also provides the option of configuring a macrocell for

combinatorial operation, with seven product terms feeding the OR func-

tion.

Again the programmable output polarity selector provides active-high or

active-low logic. The output buffer enable is controlled by the eighth

product term, allowing the macrocell to be configured for input, output, or

bidirectional functions. Feedback into the array for input or bidirectional

functions is available on all I/O pins. Macrocell Configurations for the

Registered Mode of the PEELTM 16CV8

Anachip Corp.

www.anachip.com.tw

Rev. 1.0 Dec 16, 2004

4/11

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