UPD78F0058YGC-8BT View Datasheet(PDF) - NEC => Renesas Technology
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UPD78F0058YGC-8BT Datasheet PDF : 694 Pages
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CHAPTER 4 PIN FUNCTIONS (µPD780058Y SUBSERIES) .......................................................... 66
4.1 Pin Function List ................................................................................................................. 66
4.2 Description of Pin Functions ............................................................................................ 70
4.2.1 P00 to P05, P07 (Port 0) ........................................................................................................ 70
4.2.2 P10 to P17 (Port 1) ................................................................................................................. 71
4.2.3 P20 to P27 (Port 2) ................................................................................................................. 71
4.2.4 P30 to P37 (Port 3) ................................................................................................................. 72
4.2.5 P40 to P47 (Port 4) ................................................................................................................. 73
4.2.6 P50 to P57 (Port 5) ................................................................................................................. 73
4.2.7 P60 to P67 (Port 6) ................................................................................................................. 73
4.2.8 P70 to P72 (Port 7) ................................................................................................................. 74
4.2.9 P120 to P127 (Port 12) ........................................................................................................... 74
4.2.10 P130 and P131 (Port 13) ....................................................................................................... 75
4.2.11 AVREF0 ...................................................................................................................................... 75
4.2.12 AVREF1 ...................................................................................................................................... 75
4.2.13 AVSS ......................................................................................................................................... 75
4.2.14 RESET ..................................................................................................................................... 75
4.2.15 X1 and X2 ................................................................................................................................ 75
4.2.16 XT1 and XT2 ........................................................................................................................... 75
4.2.17 VDD0, VDD1 ................................................................................................................................ 75
4.2.18 VSS0, VSS1 ................................................................................................................................. 76
4.2.19 VPP (Flash memory version only) ........................................................................................... 76
4.2.20 IC (Mask ROM version only) .................................................................................................. 76
4.3 I/O Circuits and Recommended Connection of Unused Pins....................................... 77
CHAPTER 5 CPU ARCHITECTURE ................................................................................................. 81
5.1 Memory Spaces ................................................................................................................... 81
5.1.1 Internal program memory space .............................................................................................. 87
5.1.2 Internal data memory space .................................................................................................... 89
5.1.3 Special Function Register (SFR) area .................................................................................... 89
5.1.4 External memory space ........................................................................................................... 89
5.1.5 Data memory addressing ......................................................................................................... 89
5.2 Processor Registers ........................................................................................................... 96
5.2.1 Control registers ....................................................................................................................... 96
5.2.2 General registers ...................................................................................................................... 99
5.2.3 Special-Function Registers (SFRs) ......................................................................................... 100
5.3 Instruction Address Addressing ....................................................................................... 104
5.3.1 Relative addressing .................................................................................................................. 104
5.3.2 Immediate addressing .............................................................................................................. 105
5.3.3 Table indirect addressing ......................................................................................................... 106
5.3.4 Register addressing ................................................................................................................. 107
5.4 Operand Address Addressing ........................................................................................... 108
5.4.1 Implied addressing ................................................................................................................... 108
5.4.2 Register addressing ................................................................................................................. 109
5.4.3 Direct addressing ..................................................................................................................... 110
5.4.4 Short direct addressing ............................................................................................................ 111
5.4.5 Special-Function Register (SFR) addressing .......................................................................... 113
5.4.6 Register indirect addressing .................................................................................................... 114
5.4.7 Based addressing ..................................................................................................................... 115
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User's Manual U12013EJ3V2UD
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