PIC16LCR65AT-04E/TQ View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LCR65AT-04E/TQ

8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C6X

FIGURE 4-4: PIC16C66/67 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

CALL, RETURN

13

RETFIE, RETLW

Stack Level 1

•••

Stack Level 8

Reset Vector

0000h

Peripheral Interrupt Vector 0004h

0005h

On-chip Program

Memory (Page 0)

On-chip Program

Memory (Page 1)

On-chip Program

Memory (Page 2)

On-chip Program

Memory (Page 3)

07FFh

0800h

0FFFh

1000h

17FFh

1800h

1FFFh

4.2 Data Memory Organization

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

The data memory is partitioned into multiple banks

which contain the General Purpose Registers and the

Special Function Registers. Bits RP1 and RP0 are the

bank select bits.

RP1:RP0 (STATUS<6:5>)

= 00 → Bank0

= 01 → Bank1

= 10 → Bank2

= 11 → Bank3

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers, implemented as

static RAM. All implemented banks contain special

function registers. Some “high use” special function

registers from one bank may be mirrored in another

bank for code reduction and quicker access.

4.2.1 GENERAL PURPOSE REGISTERS

These registers are accessed either directly or indi-

rectly through the File Select Register (FSR)

(Section 4.5).

For the PIC16C61, general purpose register locations

8Ch-AFh of Bank 1 are not physically implemented.

These locations are mapped into 0Ch-2Fh of Bank 0.

FIGURE 4-5: PIC16C61 REGISTER FILE

MAP

File Address

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

INDF(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

File Address

INDF(1)

80h

OPTION

81h

PCL

82h

STATUS

83h

FSR

84h

TRISA

85h

TRISB

86h

87h

88h

89h

PCLATH

8Ah

INTCON

8Bh

8Ch

General

Purpose

Register

Mapped

in Bank 0(2)

2Fh

AFh

30h

B0h

7Fh

FFh

Bank 0

Bank 1

Unimplemented data memory location; read as '0'.

Note 1: Not a physical register.

2: These locations are unimplemented in

Bank 1. Any access to these locations will

access the corresponding Bank 0 register.

DS30234D-page 20

© 1997 Microchip Technology Inc.

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