TABLE 3-3: PIC16F/LF1825/1829 MEMORY MAP, BANKS 0-7
BANK 0
BANK 1
BANK 2
BANK 3
000h
001h
002h
003h
004h
005h
006h
007h
008h
009h
00Ah
00Bh
00Ch
00Dh
00Eh
00Fh
010h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PORTA
PORTB(1)
PORTC
—
—
080h
081h
082h
083h
084h
085h
086h
087h
088h
089h
08Ah
08Bh
08Ch
08Dh
08Eh
08Fh
090h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
TRISA
TRISB(1)
TRISC
—
—
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
LATA
LATB(1)
LATC
—
—
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
ANSELA
ANSELB(1)
ANSELC
—
—
011h
PIR1
091h
PIE1
111h CM1CON0 191h
EEADRL
012h
PIR2
092h
PIE2
112h CM1CON1 192h
EEADRH
013h
—
093h
—
113h CM2CON0 193h
EEDATL
014h
—
094h
—
114h CM2CON1 194h
EEDATH
015h
TMR0
095h
OPTION
115h
CMOUT
195h
EECON1
016h
TMR1L
096h
PCON
116h
BORCON
196h
EECON2
017h
TMR1H
097h WDTCON 117h FVRCON 197h
—
018h
T1CON
098h OSCTUNE 118h DACCON0 198h
—
019h
T1GCON
099h
OSCCON
119h DACCON1 199h
RCREG
01Ah
TMR2
09Ah OSCSTAT 11Ah SRCON0 19Ah
TXREG
01Bh
01Ch
PR2
T2CON
09Bh
09Ch
ADRESL
ADRESH
11Bh
11Ch
SRCON1
—
19Bh
19Ch
SPBRGL
SPBRGH
01Dh
—
09Dh ADCON0 11Dh APFCON0 19Dh
RCSTA
01Eh CPSCON0 09Eh ADCON1 11Eh APFCON1 19Eh
TXSTA
01Fh CPSCON1 09Fh
—
11Fh
—
19Fh BAUDCON
020h
0A0h
120h
1A0h
06Fh
070h
07Fh
General
Purpose
Register
96 Bytes
0EFh
0F0h
0FFh
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
16Fh
170h
17Fh
General
Purpose
Register
80 Bytes
Accesses
70h – 7Fh
1EFh
1F0h
1FFh
General
Purpose
Register
80 Bytes(2)
Accesses
70h – 7Fh
Legend:
Note 1:
= Unimplemented data memory locations, read as ‘0’
Available only on PIC16F/LF1829.
200h
201h
202h
203h
204h
205h
206h
207h
208h
209h
20Ah
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
BANK 4
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
WPUA
WPUB(1)
WPUC
—
—
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON
SSP1CON2
SSP1CON3
—
SSP2BUF(1)
SSP2ADD(1)
SSP2MSK(1)
SSP2STAT(1)
SSP2CON(1)
SSP2CON2(1)
SSP2CON3(1)
General
Purpose
Register
80 Bytes(2)
280h
281h
282h
283h
284h
285h
286h
287h
288h
289h
28Ah
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
26Fh
270h
27Fh
Accesses
70h – 7Fh
2EFh
2F0h
2FFh
BANK 5
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
—
—
—
—
CCPR1L
CCPR1H
CCP1CON
PWM1CON
CCP1AS
PSTR1CON
—
CCPR2L
CCPR2H
CCP2CON
PWM2CON
CCP2AS
PSTR2CON
CCPTMRS
—
General
Purpose
Register
80 Bytes(2)
Accesses
70h – 7Fh
BANK 6
300h
301h
302h
303h
304h
305h
306h
307h
308h
309h
30Ah
30Bh
30Ch
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
—
380h
381h
382h
383h
384h
385h
386h
387h
388h
389h
38Ah
38Bh
38Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
—
—
—
—
CCPR3L
CCPR3H
CCP3CON
—
—
—
—
CCPR4L
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
319h
CCPR4H
399h
31Ah CCP4CON 39Ah
31Bh
—
39Bh
31Ch
—
39Ch
31Dh
—
39Dh
31Eh
—
39Eh
31Fh
320h
32Fh
—
General Purpose
Register
16 Bytes(2)
39Fh
3A0h
330h
36Fh
370h
Unimplemented
Read as ‘0’)
Accesses
70h – 7Fh
3EFh
3F0h
37Fh
3FFh
BANK 7
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
INLVLA
INLVLB(1)
INLVLC
—
—
IOCAP
IOCAN
IOCAF
IOCBP(1)
IOCBN(1)
IOCBF(1)
—
—
—
CLKRCON
—
MDCON
MDSRC
MDCARL
MDCARH
Unimplemented
Read as ‘0’
Accesses
70h – 7Fh