PIC16F84A-10B/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F84A-10B/SS Datasheet PDF : 124 Pages
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PIC16F8X
TABLE 4-1 REGISTER FILE SUMMARY
Address Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note3)
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
INDF
TMR0
PCL
STATUS (2)
FSR
PORTA
PORTB
EEDATA
EEADR
0Ah
PCLATH
0Bh
INTCON
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
Low order 8 bits of the Program Counter (PC)
IRP
RP1
RP0
TO
PD
Z
DC
Indirect data memory address pointer 0
—
—
—
RA4/T0CKI
RA3
RA2
RA1
RB7
RB6
RB5
RB4
RB3
RB2
RB1
Unimplemented location, read as '0'
EEPROM data register
EEPROM address register
—
—
—
Write buffer for upper 5 bits of the PC (1)
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
---- ----
xxxx xxxx
0000 0000
C
RA0
RB0/INT
0001 1xxx
xxxx xxxx
---x xxxx
xxxx xxxx
---- ----
xxxx xxxx
xxxx xxxx
RBIF
---0 0000
0000 000x
---- ----
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
---u uuuu
uuuu uuuu
---- ----
uuuu uuuu
uuuu uuuu
---0 0000
0000 000u
Bank 1
80h
INDF
Uses contents of FSR to address data memory (not a physical register)
---- ---- ---- ----
81h
OPTION_
REG
RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
82h
PCL
Low order 8 bits of Program Counter (PC)
0000 0000 0000 0000
83h
STATUS (2)
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
84h
FSR
Indirect data memory address pointer 0
xxxx xxxx uuuu uuuu
85h
TRISA
—
—
— PORTA data direction register
---1 1111 ---1 1111
86h
TRISB
PORTB data direction register
1111 1111 1111 1111
87h
Unimplemented location, read as '0'
---- ---- ---- ----
88h
EECON1
—
—
—
EEIF
WRERR WREN WR
RD
---0 x000 ---0 q000
89h
EECON2
EEPROM control register 2 (not a physical register)
---- ---- ---- ----
0Ah
PCLATH
—
—
—
Write buffer for upper 5 bits of the PC (1)
---0 0000 ---0 0000
0Bh
INTCON
GIE
EEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition.
The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents
of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never trans-
ferred to PCLATH.
The TO and PD status bits in the STATUS register are not affected by a MCLR reset.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30430C-page 14
© 1998 Microchip Technology Inc.
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