PIC16F720 View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16F720 Datasheet PDF : 254 Pages
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PIC16(L)F720/721
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 1
80h( 2)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx xxxx xxxx
81h
82h( 2)
83h( 2)
84h( 2)
85h(5)
OPTION_
REG
PCL
STATUS
FSR
TRISA
RABPU
IRP
—
INTEDG
RP1
—
T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 1111 1111
Program Counter (PC) Least Significant Byte
RP0
TO
PD
Z
Indirect Data Memory Address Pointer
TRISA5
TRISA4
—(4)
TRISA2
DC
TRISA1
C
TRISA0
0000 0000
0001 1xxx
xxxx xxxx
--11 -111
0000 0000
000q quuu
uuuu uuuu
--11 -111
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
—
—
—
—
1111 ---- 1111 ----
87h
TRISC
TRISC7 TRISC6
TRISC5
TRISC4
TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
88h
—
Unimplemented
—
—
89h
—
8Ah( 1),( 2) PCLATH
—
8Bh( 2)
INTCON
GIE
—
PEIE
—
TMR0IE
Unimplemented
Write Buffer for the upper 5 bits of the Program Counter
INTE
RABIE TMR0IF INTF
RABIF
—
—
---0 0000 ---0 0000
0000 000x 0000 000x
8Ch
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh
—
Unimplemented
—
—
8Eh
PCON
—
—
—
—
—
—
POR
BOR ---- --qq ---- --uu
8Fh
T1GCON TMR1GE T1GPOL
T1GTM
T1GSPM T1GGO/ T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
DONE
90h
OSCCON
—
—
IRCF1
IRCF0
ICSL
ICSS
—
—
--10 qq-- --10 qq--
91h
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0 --00 0000 --uu uuuu
92h
PR2
Timer2 module Period Register
1111 1111 1111 1111
93h
93h( 3)
SSPADD
SSPMSK
ADD<7:0>
MSK<7:0>
0000 0000 0000 0000
1111 1111 1111 1111
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
95h
WPUA
—
—
WPUA5
WPUA4
WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111
96h
IOCA
—
—
IOCA5
IOCA4
IOCA3
IOCA2 IOCA1 IOCA0 --00 0000 --00 0000
97h
—
Unimplemented
—
—
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH TRMT
TX9D 0000 -010 0000 -010
99h
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0 0000 0000 0000 0000
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
FVRCON FVRRDY FVREN
TSEN
TSRNG
—
—
ADFVR1 ADFVR0 q000 --00 q000 --00
9Eh
—
Unimplemented
—
—
9Fh
ADCON1
—
ADCS2
ADCS1
ADCS0
—
—
—
—
-000 ---- -000 ----
Legend:
Note 1:
2:
3:
4:
5:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
This bit is unimplemented and reads as ‘1’.
See Register 6-2.
2010-2013 Microchip Technology Inc.
DS41430D-page 17
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