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723T View Datasheet(PDF) - Microchip Technology

Part Name
Description
Manufacturer
723T Datasheet PDF : 302 Pages
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PIC16F72X/PIC16LF72X
TABLE 2:
40/44-PIN PDIP/TQFP/QFN SUMMARY (PIC16F724/727/PIC16LF724/727)
I/O
40-Pin 44-Pin 44-Pin
PDIP TQFP QFN
A/D
Cap
Sensor
Timers
CCP
AUSART
SSP
Interrupt Pull-Up
Basic
RA0
2
19
19
AN0
SS(3)
RA1
3
20
20
AN1
VCAP(4)
RA2
4
21
21
AN2
RA3
5
22
22 AN3/VREF
RA4
6
23
23
CPS6 T0CKI
RA5
7
24
24
AN4
CPS7
RA6 14
31
33
RA7 13
30
32
SS(3)
VCAP(4)
OSC2/CLKOUT/VCAP(4)
OSC1/CLKIN
RB0 33
8
9
AN12 CPS0
IOC/INT
Y
RB1 34
9
10
AN10 CPS1
IOC
Y
RB2 35
10
11
AN8
CPS2
IOC
Y
RB3 36
11
12
AN9
CPS3
CCP2(2)
IOC
Y
RB4 37
14
14
AN11 CPS4
IOC
Y
RB5 38
15
15
AN13 CPS5 T1G
IOC
Y
RB6 39
16
16
RB7 40
17
17
IOC
Y
ICSPCLK/ICDCLK
IOC
Y
ICSPDAT/ICDDAT
RC0 15
32
34
— T1OSO/ —
T1CKI
RC1 16
35
35
T1OSI CCP2(2)
RC2 17
36
36
CCP1
RC3 18
37
37
SCK/SCL
RC4 23
42
42
SDI/SDA
RC5 24
43
43
SDO
RC6 25
44
44
TX/CK
RC7 26
1
1
RX/DT
RD0 19
38
38
CPS8
RD1 20
39
39
CPS9
RD2 21
40
40
CPS10 —
RD3 22
41
41
CPS11 —
RD4 27
2
2
CPS12 —
RD5 28
3
3
CPS13 —
RD6 29
4
4
CPS14 —
RD7 30
5
5
CPS15 —
RE0
8
25
25
AN5
RE1
9
26
26
AN6
RE2 10
27
27
AN7
RE3
1
18
18
Y(1)
— 11,32 7,20 7,8,28
— 12,13 6,29 6,30,31 —
MCLR/VPP
VDD
VSS
Note 1:
2:
3:
4:
Pull-up enabled only with external MCLR configuration.
RC1 is the default pin location for CCP2. RB3 may be selected by changing the CCP2SEL bit in the APFCON register.
RA5 is the default pin location for SS. RA0 may be selected by changing the SSSEL bit in the APFCON register.
PIC16F72X devices only.
Note:
The PIC16F72X devices have an internal low dropout voltage regulator. An external capacitor must be
connected to one of the available VCAP pins to stabilize the regulator. For more information, see
Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF72X devices do not have the voltage
regulator and therefore no external capacitor is required.
DS41341E-page 10
© 2009 Microchip Technology Inc.

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