HI1396Y View Datasheet(PDF) - Intersil

Part Name

Description

Manufacturer

HI1396Y

8-Bit, 125 MSPS Flash A/D Converter

Intersil 

Timing Diagram

HI1396Y

ANALOG IN

CLK

CLK

N

TPW1

TPW0

N+1

N+2

DIGITAL OUT

TOD

N-1

80%

20%

N

TR

FIGURE 1.

20%

N+1

80%

TF

Pad Descriptions

PAD

NUMBER SYMBOL I/O

50, 53,

AGND

-

55, 58

STANDARD

VOLTAGE

LEVEL

0V

EQUIVALENT CIRCUIT

47, 48,

AVEE

-

60, 61

-5.2V

39

CLK

I

38

CLK

ECL

DGND1

CLK

CLK

R

R

R

R

DESCRIPTION

Analog GND. Used as GND for in-

put buffers and latches of compara-

tors. Isolated from DGND.

Analog VEE -5.2V (Typ.). Internally

connected to DVEE (Resistance: 4Ω

to 6Ω). Bypass with 0.1µF to AGND.

CLK Input

Input complementary to CLK. When

left open pulled down to -1.3V. De-

vice is operable without CLK input,

but use of complementary inputs of

CLK and CLK is recommended to

obtain stable high speed operation.

DVEE

9, 11,

DGND

-

27, 29

8, 30

DVEE

-

0V

-5.2V

RR

4

Digital GND.

Digital VEE. Internally connected to

AVEE (resistance: 4Ω to 6Ω). By-

pass with 0.1µF to DGND

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