PIC16F1513 View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16F1513

28-Pin Flash Microcontrollers with XLP Technology

Microchip Technology 

TABLE 3-5: PIC16(L)F1512/3 MEMORY MAP (BANKS 8-30)

BANK 8

BANK 9

BANK 10

BANK 11

400h

40Bh

40Ch

46Fh

470h

47Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

480h

48Bh

48Ch

4EFh

4F0h

4FFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

500h

50Bh

50Ch

56Fh

570h

57Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

580h

58Bh

58Ch

5EFh

5F0h

5FFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

600h

60Bh

60Ch

66Fh

670h

67Fh

BANK 12

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

BANK 13

680h

68Bh

68Ch

6EFh

6F0h

6FFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

700h

70Bh

70Ch

76Fh

770h

77Fh

BANK 14

Core Registers

(Table 3-2)

See Table 3-6

Common RAM

(Accesses

70h – 7Fh)

BANK 15

780h

78Bh

78Ch

7EFh

7F0h

7FFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

BANK 16

BANK 17

BANK 18

BANK 19

BANK 20

BANK 21

BANK 22

BANK 23

800h

80Bh

80Ch

86Fh

870h

87Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

880h

88Bh

88Ch

8EFh

8F0h

8FFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

900h

90Bh

90Ch

96Fh

970h

97Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

980h

98Bh

98Ch

9EFh

9F0h

9FFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

A00h

A0Bh

A0Ch

A6Fh

A70h

A7Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

A80h

A8Bh

A8Ch

AEFh

AF0h

AFFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

B00h

B0Bh

B0Ch

B6Fh

B70h

B7Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

B80h

B8Bh

B8Ch

BEFh

BF0h

BFFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

BANK 24

BANK 25

BANK 26

BANK 27

BANK 28

BANK 29

BANK 30

BANK 31

C00h

C0Bh

C0Ch

C6Fh

C70h

C7Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

C80h

C8Bh

C8Ch

CEFh

CF0h

CFFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

D00h

D0Bh

D0Ch

D6Fh

D70h

D7Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

D80h

D8Bh

D8Ch

DEFh

DF0h

DFFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

E00h

E0Bh

E0Ch

E6Fh

E70h

E7Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

E80h

E8Bh

E8Ch

EEFh

EF0h

EFFh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

F00h

F0Bh

F0Ch

F6Fh

F70h

F7Fh

Core Registers

(Table 3-2)

Unimplemented

Read as ‘0’

Common RAM

(Accesses

70h – 7Fh)

F80h

F8Bh

F8Ch

FEFh

FE0h

FEFh

Core Registers

(Table 3-2)

See (Table 3-7)

Common RAM

(Accesses

70h – 7Fh)

Legend:

= Unimplemented data memory locations, read as ‘0’.

Share Link: