PLL102-15 View Datasheet(PDF) - PhaseLink Corporation

Part Name

Description

Manufacturer

PLL102-15

Low Skew Output Buffer

PhaseLink Corporation 

3. Switching Characteristics

PARAMETERS

Output Frequency

Duty Cycle ( t2 ÷ t1 )

Duty Cycle ( t2 ÷ t1 )

Rise Time

Fall Time

Output to Output Skew

Delay, REF Rising Edge to

CLKOUT Rising Edge

Device to Device Skew

Cycle to Cycle Jitter

PLL Lock Time

Jitter; Absolute Jitter

Jitter; 1- sima

SYMBOL

DESCRIPTION

t1

Dt1

Measured at 1.4V,

C L=30pF, Fout = 60MHz

Dt2

Measured at 1.4V

Tr

Measured between 0.8V

and 2.0V, C L=30pF

Tf

Measured between 2.0V

and 0.8V, C L=30pF

T skew

All outputs equally loaded,

C L=20p F

T delay

Measured at 1.4V

T dsk -dsk

T cyc -cyc

T loc k

T jabs

T j1 -s

Measured at VDD/2 on the

CLKOUT pins of devices

Loaded outputs

Stable power supply, valid

clock presented on REF pin

At 10,000 cycles, CL=30pF

At 10,000 cycles, CL=30pF

PLL102-15

Low Skew Output Buffer

MIN.

25

40.0

45.0

-100

TYP.

50.0

50.0

1.2

1.2

0

0

70

14

MAX.

60

60.0

55.0

1.5

1.5

250

±350

700

200

1.0

100

30

UNITS

MHz

%

%

ns

ns

ps

ps

ps

ps

ms

ps

ps

SWITCHING WAVEFORMS

Duty Cycle Timing

t1

t2

1.4V

1.4V

1.4V

Output - Output Skew

1.4V

Output

Output

1.4V

T SKEW

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 05/06/03 Page 4

Share Link: