PLL103-53 View Datasheet(PDF) - PhaseLink Corporation
Part Name
Description
Manufacturer
PLL103-53 Datasheet PDF : 7 Pages
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Preliminary PLL103-53
DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS
3. Electrical Specifications (Continued)
PARAMETERS SYMBOL
Supply Current
(DDR-only mode)
Supply Current
(SDRAM mode)
Supply Current
Output Crossing
Voltage
Output Voltage
Swing
Duty Cycle
Max. Operating
Frequency
Rising Edge Rate
Falling Edge Rate
Clock Skew ( pin to
pin )
Stabilization Time
IDD
IDD
IDDS
VOC
VOUT
DT
TOR
TOF
TSKEW
TST
Note: TBM: To be measured
CONDITIONS
Unloaded outputs, 133MHz
Unloaded outputs, 133MHz
PD = 0
Measured @ 1.5V
Measured @
Measured @
0.4V ~ 2.4V
2.4V ~ 0.4V
All outputs equally loaded
MIN.
(VDD/2)
-0.1
1.1
45
66
1.0
1.0
TYP.
VDD/2
50
1.5
1.5
MAX.
TBM
TBM
TBM
(VDD/2)+
0.1
VDD-0.4
55
170
2.0
2.0
100
0.1
UNITS
mA
mA
mA
V
V
%
MHz
V/ns
V/ns
ps
ms
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/01/00 Page 6
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