PLS159 View Datasheet(PDF) - Philips Electronics

Part Name

Description

Manufacturer

PLS159

Programmable logic sequencer (16 × 45 × 12)

Philips Electronics 

Philips Semiconductors Programmable Logic Devices

Programmable logic sequencer

(16 × 45 × 12)

Product specification

PLS159A

DESCRIPTION

The PLS159A is a 3-State output, registered

logic element combining AND/OR gate arrays

with clocked J-K flip-flops. These J-K

flip-flops are dynamically convertible to

D-type via a “fold-back” inverting buffer and

control gate FC. It features 8 registered I/O

outputs (F) in conjunction with 4 bidirectional

I/O lines (B). These yield variable I/O gate

and register configurations via control gates

(D, L) ranging from 16 inputs to 12 outputs.

The AND/OR arrays consist of 32 logic AND

gates, 13 control AND gates, and 21 OR

gates with fusible link connections for

programming I/O polarity and direction. All

AND gates are linked to 4 inputs (I),

bidirectional I/O lines (B), internal flip-flop

outputs (Q), and Complement Array output

(C). The Complement Array consists of a

NOR gate optionally linked to all AND gates

for generating and propagating

complementary AND terms.

On-chip T/C buffers couple either True (I, B,

Q) or Complement (I, B, Q, C) input polarities

to all AND gates, whose outputs can be

optionally linked to all OR gates. Any of the

32 AND gates can drive bidirectional I/O lines

(B), whose output polarity is individually

programmable through a set of Ex-OR gates

for implementing AND-OR or AND-NOR logic

functions. Similarly, any of the 32 AND gates

can drive the J-K inputs of all flip-flops. There

are 4 AND gates for the Asynchronous

Preset/Reset functions.

All flip-flops are positive edge-triggered and

can be used as input, output or I/O (for

interfacing with a bidirectional data bus) in

conjunction with load control gates (L),

steering inputs (I), (B), (Q) and

programmable output select lines (E).

The PLS159A is field-programmable,

enabling the user to quickly generate custom

patterns using standard programming

equipment.

FEATURES

• High-speed version of PLS159

• fMAX = 18MHz

– 25MHz clock rate

• Field-Programmable (Ni-Cr link)

• 4 dedicated inputs

• 13 control gates

• 32 AND gates

• 21 OR gates

• 45 product terms:

– 32 logic terms

– 13 control terms

• 4 bidirectional I/O lines

• 8 bidirectional registers

• J-K, T, or D-type flip-flops

• Power-on reset feature on all flip-flops

(Fn = 1)

• Asynchronous Preset/Reset

• Complement Array

• Active-High or -Low outputs

• Programmable OE control

• Positive edge-triggered clock

• Input loading: –100µA (max.)

• Power dissipation: 750mW (typ.)

• TTL compatible

• 3-State outputs

APPLICATIONS

• Random sequential logic

• Synchronous up/down counters

• Shift registers

• Bidirectional data buffers

• Timing function generators

• System controllers/synchronizers

• Priority encoder/registers

ORDERING INFORMATION

DESCRIPTION

20-Pin Plastic Dual In-Line Package (300mil-wide)

20-Pin Plastic Leaded Chip Carrier

ORDER CODE

PLS159AN

PLS159AA

PIN CONFIGURATIONS

N Package

CLK 1

I0 2

I1 3

I2 4

I3 5

B0 6

B1 7

B2 8

B3 9

GND 10

20 VCC

19 F7

18 F6

17 F5

16 F4

15 F3

14 F2

13 F1

12 F0

11 OE

N = Plastic Dual In-Line Package (300mil-wide)

A Package

I1 I0 CLK VCCF7

3 2 1 20 19

I2 4

18 F6

I3 5

17 F5

B0 6

16 F4

B1 7

15 F3

B2 8

14 F2

9 10 11 12 13

B3 GND OE F0 F1

A = Plastic Leaded Chip Carrier

DRAWING NUMBER

0408D

0400E

October 22, 1993

25

853–1159 11164

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