Philips Semiconductors Programmable Logic Devices
Programmable logic sequencer
(16 ร 45 ร 12)
Product specification
PLS159A
FUNCTIONAL DIAGRAM
(LOGIC TERMS)
a
b
(CONTROL TERMS)
PB RB PA RA
LB LA D
EA EB
a
OE
a
b
b
Q
Q
C
C
S
X
B
PR
JQ
F
M
(4)
K
CK
M
T31
T0 FC
PR
JQ
(4)
K
CK
CK
F
CLK
LOGIC FUNCTION
Q3 Q2 Q1 Q0
10 1 0
STATE REGISTER
SR PRESENT STATE
Aโ
Bโ
Cโ
...
0 0 0 1 Sn + 1 NEXT STATE
โ
SET Q0: J0 = (Q3 Q2 โ
Q1 โ
Q0) โ
A โ
B โ
C . . .
K0 = 0
RESET
Q1:
J1
K1
=
=
0
(Q3โ
Q2
โ
Q1
โ
Q0)
โ
A
โ
B
โ
C
.
.
.
HOLD Q2: J2 = 0
K2 = 0
TOGGLE Q3: J3 = (Q3 โ
Q2 โ
Q1 โ
Q0) โ
A โ
B โ
C . . .
K3 = (Q3โ
Q2 โ
Q1 โ
Q0) โ
A โ
B โ
C . . .
NOTE:
Similar logic functions are applicable for D
and T mode flip-flops.
FLIP-FLOP TRUTH TABLE
OE L CK P R J K Q F
H
Hi-Z
L X X L XX XL H
L X X H LX XH L
L X X L HX XL H
L L โ L L L LQ Q
L L โ L LL HL H
L L โ L LH LH L
L L โ L L H HQ Q
H H โ L L L H L H*
H H โ L L H L H L*
+10V X โ X X L H L H* *
X โ X X H L H L* *
NOTES:
1. Positive Logic:
J-K = T0 + T1 + T2 โฆโฆโฆโฆโฆโฆ T31
Tn = Cโ
(I0 โ
I1 โ
I2 โฆ) โ
(Q0 โ
Q1 โฆ) โ
(B0 โ
B1 โ
โฆ)
2. โ denotes transition from Low to High level.
3. X = Donโt care
4. * = Forced at Fn pin for loading the J-K
flip-flop in the Input mode. The load
control term, Ln must be enabled (HIGH)
and the p-terms that are connected to the
associated flip-flop must be forced LOW
(disabled) during Preload.
5. At P = R = H, Q = H. The final state of Q
depends on which is released first.
6. * * = Forced at Fn pin to load J-K flip-flop
independent of program code (Diagnostic
mode), 3-State B outputs.
October 22, 1993
27