PSD914F3-90 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD914F3-90 Datasheet PDF : 93 Pages
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Preliminary Information
PSD4000 Series
8.0
Register Bit
Definition
(cont.)
Flash Boot Protection Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Security_Bit
*
*
*
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit definitions:
Sec<i>_Prot 1 = Boot Block Sector <i> is write protected.
Sec<i>_Prot 0 = Boot Block Sector <i> is not write protected.
Security_Bit 0 = Security Bit in device has not been set.
1 = Security Bit in device has been set.
Page Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pgr7
Pgr6
Pgr5
Pgr4
Pgr3
Pgr2
Pgr1
Pgr0
Bit definitions:
Configure Page input to PLD. Default Pgr[7:0] = 00.
PMMR0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
*
*
PLD
PLD
PLD
Mcells clk array-clk Turbo
*Not used bit should be set to zero.
Bit definitions: (default is 0)
Bit 1 0 = Automatic Power Down (APD) is disabled.
1 = Automatic Power Down (APD) is enabled.
*
APD
enable
Bit 3 0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
Bit 4 0 = CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
Bit 5 0 = CLKIN input to the PLD Micro⇔Cells is connected.
1 = CLKIN input to the PLD Micro⇔Cells is disconnected, saving power.
Bit 0
*
PMMR2 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
PLD
PLD
PLD
PLD
PLD
*
*
array WRh array Ale array Cntl2 array Cntl1 array Cntl0
*Not used bit should be set to zero.
Bit definitions (defauld is 0):
Bit 0 0 = Address A[7:0] are connected into the PLD array.
1 = Address A[7:0] are blocked from the PLD array, saving power.
Note: in XA mode, A3-0 come from PF3-0 and A7-4 come from ADIO7-4.
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to the PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to the PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to the PLD AND array is disconnected, saving power.
Bit 5 0 = Ale input to the PLD AND array is connected.
1 = Ale input to the PLD AND array is disconnected, saving power.
Bit 6 0 = WRh/DBE input to the PLD AND array is connected.
1 = WRh/DBE input to the PLD AND array is disconnected, saving power.
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