PSD4235F1-12B81 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD4235F1-12B81 Datasheet PDF : 93 Pages
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Preliminary Information
PSD4000 Series
2.0
Key Features
t A simple interface to 16-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by
the microcontroller automatically when the address is decoded and a read or write is
performed. A partial list of the MCU families supported include:
• Intel 80196, 80296, 80186, and 80386EX
• Motorola 68HC16, 68HC12, 683XX, and MC2001
• Philips 80C51XA
• Infineon C16X devices
• Hitachi H8
t 4 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
t Internal secondary 256 Kbit Flash boot memory. It is divided into four equal-sized
blocks that can be accessed with user-specified addresses. This secondary memory
brings the ability to execute code and update the main Flash concurrently.
t 64 Kbit SRAM. The SRAM’s contents can be protected from a power failure by
connecting an external battery.
t General Purpose PLD (GPLD) with 24 outputs. The GPLD may be used to implement
external chip selects or combinatorial logic function.
t Decode PLD (DPLD) that decodes address for selection of internal memory blocks.
t 52 individually configurable I/O port pins that can be used for the following functions:
• MCU I/Os
• PLD I/Os
• Latched MCU address output
• Special function I/Os.
• I/O ports may be configured as open-drain outputs.
t Standby current as low as 50 µA for 5 V devices.
t Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
t Internal page register that can be used to expand the microcontroller address space
by a factor of 256.
t Internal programmable Power Management Unit (PMU) that supports a low power
mode called Power Down Mode. The PMU can automatically detect a lack of
microcontroller activity and put the PSD4000 into Power Down Mode.
t Erase/Write cycles:
• Flash memory – 100,000 minimum
• PLD – 1,000 minimum
• 15 year data retention
3.0 PSD4000
Series
Table 1. PSD4000 Product Matrix
Part #
PSD4000
Series
Device
Flash
Serial ISP
I/O PLD Input
Output PLD JTAG/ISP
Pins Inputs Macrocells Macrocells Outputs Port
Flash
Main
Memory
Kbit
8 Sectors
Boot
Memory
Kbit
(4 Sectors)
SRAM
Kbit
Supply
Voltage
PSD4000 PSD4135G2 52 66
PSD4235G2* 52 82
24
24
Yes
4096
256
64
5V
16
24
Yes
4096
256
64
5V
*See PSD4235G2 Data Sheet.
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