ST92195B3T1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST92195B3T1 Datasheet PDF : 22 Pages
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ST92195B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
RESET Reset (input, active low). The ST9+ is ini-
tialised by the Reset signal. With the deactivation
of RESET, program execution begins from the
Program memory location pointed to by the vector
contained in program memory locations 00h and
01h.
R/G/B Red/Green/Blue. Video color analog DAC
outputs.
FB Fast Blanking. Video analog DAC output.
VDD Main power supply voltage (5V±10%, digital)
WSCF, WSCR Analog pins for the VPS/WSS slic-
er . These pins must be tied to ground or not con-
nected.
VPP: On EPROM/OTP devices, the WSCR pin is
replaced by VPP which is the programming voltage
pin. VPP should be tied to GND in user mode.
MCFM Analog pin for the display pixel frequency
multiplier.
OSCIN, OSCOUT Oscillator (input and output).
These pins connect a parallel-resonant crystal
(24MHz maximum), or an external source to the
on-chip clock oscillator and buffer. OSCIN is the
input of the oscillator inverter and internal clock
generator; OSCOUT is the output of the oscillator
inverter.
Figure 3. 56-Pin Package Pin-Out
INT7/P2.0 1
RESET 2
P0.7 3
P0.6 4
P0.5 5
P0.4 6
P0.3 7
AIN4/P0.2 8
P0.1 9
P0.0 10
CSO/RE SET0/P3.7 11
P3.6 12
P3.5 13
P3.4 14
B 15
G 16
R 17
FB 18
SDI/SDO/ P5.1 19
SCK/INT2/P5. 0 20
VDD 21
JTDO 22
WSCF 23
VPP/WSCR 24
AVDD3 25
TEST 0 26
MCFM 27
JTCK 28
VSYNC Vertical Sync. Vertical video synchronisa-
tion input to OSD. Positive or negative polarity.
HSYNC/CSYNC Horizontal/Composite sync. Hori-
zontal or composite video synchronisation input to
OSD. Positive or negative polarity.
PXFM Analog pin for the Display Pixel Frequency
Multiplier
AVDD3 Analog VDD of PLL. This pin must be tied
to VDD externally.
GND Digital circuit ground.
AGND Analog circuit ground (must be tied exter-
nally to digital GND).
CVBS1 Composite video input signal for the Tele-
text slicer and sync extraction.
CVBS2 Composite video input signal for the VPS/
WSS slicer. Pin AC coupled.
AVDD1, AVDD2 Analog power supplies (must be
tied externally to AVDD3).
TXCF Analog pin for the Teletext slicer line PLL.
CVBSO, JTDO, JTCK Test pins: leave floating.
TEST0 Test pins: must be tied to AVDD2.
JTRST0 Test pin: must be tied to GND.
56 P2.1/INT5/AIN1
55 P2.2/INT0/AIN2
54 P2.3/INT6/VS01
53 P2.4/NMI
52 P2.5/AIN3/INT4/VS02
51 OSCIN
50 OSCOUT
49 P4.7/PWM7/EX TRG/ST OUT
48 P4.6/PWM6
47 P4.5/PWM5
46 P4.4/PWM4
45 P4.3/PWM3/TSLU/HT
44 P4.2/PWM2
43 P4.1/PWM1
42 P4.0/PWM0
41 VSYNC
40 HSYNC/CSYNC
39 AVDD1
38 PXFM
37 JTRSTO
36 GND
35 AGND
34 CVBS1
33 CVBS2
32 JTMS
31 AVDD2
30 CVBSO
29 TXCF
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