UPD784225YGK-XXX-9EU View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD784225YGK-XXX-9EU Datasheet PDF : 92 Pages
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µPD784224, 784225, 784224Y, 784225Y
Table 7-1. Port Functions
Port Name
Pin Name
Function
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 12
Port 13
P00 to P05 • Can be set in input or output mode bit-wise
P10 to P17 • Input port
P20 to P27 • Can be set in input or output mode bit-wise
P30 to P37 • Can be set in input or output mode bit-wise
P40 to P47
• Can be set in input or output mode bit-wise
• Can directly drive LEDs
P50 to P57
• Can be set in input or output mode bit-wise
• Can directly drive LEDs
P60 to P67 • Can be set in input or output mode bit-wise
P70 to P72 • Can be set in input or output mode bit-wise
P120 to P127 • Can be set in input or output mode bit-wise
P130, P131 • Can be set in input or output mode bit-wise
Specification of Pull-up Resistor
Connection by Software
Can be specified bit-wise
—
Can be specified bit-wise
Can be specified bit-wise
Can be specified in 1-port units
Can be specified in 1-port units
Can be specified in 1-port units
Can be specified bit-wise
Can be specified bit-wise
—
7.2 Clock Generator
An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider.
If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider
to reduce the current consumption.
Figure 7-2. Block Diagram of Clock Generator
XT1
Subsystem
clock
fXT
XT2
oscillator
X1
Main system
clock
IDLE fX
X2
oscillator
controller
STOP and bit 2 (MCK) of the
standby control register (STBC)
= 1 when the subsystem clock
is selected as CPU clock
Frequency
divider fX
2
Prescaler
fXX
fXX fXX fXX
2 22 23
Prescaler
Watch timer,
clock output
function
Clock to
peripheral
hardware
STOP,
IDLE
controller
HALT
controller
CPU
clock
(fCPU)
Internal
system
clock
(fCLK)
Data Sheet U12376EJ1V0DS00
31
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