PSD913G3-C-90JI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
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PSD913G3-C-90JI Datasheet PDF : 94 Pages
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Preliminary Information
PSD9XX Family
The
PSD9XX
Functional
Blocks
(cont.)
9.1.1.4 Power-Up Condition
The PSD9XX Flash memory is reset upon power-up to the read array mode. The FSi and
CSBOOTi select signals, along with the write strobe signal, must be in the false state
during power-up for maximum security of the data contents and to remove the possibility of
a byte being written on the first edge of a write strobe signal. Any write cycle initiation is
locked when VCC is below VLKO.
9.1.1.5 Read
Under typical conditions, the microcontroller may read the Flash, or Secondary Flash
memories using read operations just as it would a ROM or RAM device. Alternately, the
microcontoller may use read operations to obtain status information about a program or
erase operation in progress. Lastly, the microcontroller may use instructions to read
special data from these memories. The following sections describe these read functions.
9.1.1.5.1 Read the Contents of Memory
Main Flash and Secondary Flash memories are placed in the read array mode after
power-up, chip reset, or a Reset Flash instruction (see Table 9). The microcontroller can
read the memory contents of main Flash or Secondary Flash by using read operations any
time the read operation is not part of an instruction sequence.
9.1.1.5.2 Read the Main Flash Memory Identifier
The main Flash memory identifier is read with an instruction composed of 4 operations:
3 specific write operations and a read operation (see Table 9). During the read operation,
address bits A6, A1, and A0 must be 0,0,1, respectively, and the appropriate sector select
signal (FSi) must be active. The PSD9XX main Flash memory ID is E7h (PSD934/954F2)
and E4h (PSD913F2).
9.1.1.5.3 Read the Flash Memory Sector Protection Status
The Flash memory sector protection status is read with an instruction composed of 4
operations: 3 specific write operations and a read operation (see Table 9). During the read
operation, address bits A6, A1, and A0 must be 0,1,0, respectively, while the chip select
(FSi or CSBOOTi) designates the Flash sector whose protection has to be verified. The
read operation will produce 01h if the Flash sector is protected, or 00h if the sector is not
protected.
The sector protection status for all NVM blocks (main Flash or Secondary Flash) can also
be read by the microcontroller accessing the Flash Protection and Secondary Flash
Protection registers in PSD I/O space. See section 9.1.1.9.1 for register definitions.
9.1.1.5.4 Read the Erase/Program Status Bits
The PSD9XX provides several status bits to be used by the microcontroller to confirm
the completion of an erase or programming instruction of Flash memory. These status bits
minimize the time that the microcontroller spends performing these tasks and are defined
in Table 10. The status bits can be read as many times as needed.
Table 10. Status Bits
FSi/
CSBOOTi DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Data Toggle Error
Erase
Flash
VIH Polling Flag Flag
X Time- X
X
X
out
NOTES: 1. X = Not guaranteed value, can be read either 1 or 0.
2. DQ7-DQ0 represent the Data Bus bits, D7-D0.
3. FSi/CSBOOTi are active high.
For Flash memory, the microcontroller can perform a read operation to obtain these status
bits while an erase or program instruction is being executed by the embedded algorithm.
See section 9.1.1.7 for details.
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