Q67007-A9689 View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

Q67007-A9689

Dual Low Drop Voltage Regulator

Infineon Technologies 

TLE 7469

VI

t

VQ1

V

RT1

t

V

Q2

V

RT2

TRR

T RR

t

VRO

T RD

TRD

T RD

VROH

VROL

Figure 5 Reset Function and Timing Diagram

t

A E T03532.V S D

Watchdog Operation

The watchdog uses a fraction of the charge pump oscillator’s clock signal as timebase.

Connecting the DT pin to Q1 or to Q2 the watchdog timebase can be adjusted. The

watchdog can be turned off by a low level (VDT ≤ 0.8 V) applied to the DT pin. The timing

values used in this text refer to typ. values with DT connected to Q1 (fast timing).

Figure 6 shows the state diagram of the window watchdog (WWD). After power-on, the

reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay

time TRD of typ. 8 ms. With the LOW to HIGH transition of the signal at RO the device

starts the ignore window time tCW (32 ms). During this window the signal at the WDI pin

is ignored. Next the WWD starts the open window. When a valid trigger signal is detected

during the open window a closed window is initialized immediately. A trigger signal within

Final Data Sheet

16

Rev. 1.3, 2004-10-28

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