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QT1100A-ISG View Datasheet(PDF) - Quantum Research Group

Part Name
Description
Manufacturer
QT1100A-ISG
Quantum
Quantum Research Group Quantum
QT1100A-ISG Datasheet PDF : 42 Pages
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AKS works for keys located anywhere and is not restricted to
physically adjacent keys; the device has no knowledge of
which keys are actually physically adjacent. When enabled
for a key, adjacent key suppression causes detections on
that key to be suppressed if any other AKS-enabled key has
a more negative signal deviation from its reference.
AKS will not function if NDIL = 1 for the key. The AKS feature
requires 2 or more scans of all keys to function, hence NDIL
must be 2 or greater.
4.7 EK - Error Key Control Bits
Bytes 20 - 29, Bit 5
Default value:
0 (off)
The EK function allows one or more keys to be forced into
detection artificially if there is a major error anywhere in the
device including on any key. The key to be forced active is
selected per-key by the EK bit; any or all 10 keys can be
enabled for this function if desired. The reporting of the
forced key is via any interface method - scanport, UART, or
SPI, as well as the LED pin if the K2L mode for the chosen
key is enabled; note however that major errors force the LED
pin active regardless of the EK function.
The EK function allows error reporting via a redundant path
for failure detection purposes, to make key sensing more
robust.
See also Section 3.5.7.
4.8 K2L / LEDP / KEYO Control Bits
K2L: Bytes 20 - 29, Bit 4 (one per key)
LEDP: Byte 32, Bit 3
KEYO: Byte 34, Bit 7
Default K2L value:
0 (off)
Default LEDP value:
0 (active low)
Default KEYO value: 0 (off)
The LED pin can be used as a health indicator, key detect
indicator, and an error status. This pin can act as a backup
information source for a host microcontroller to provide for
redundant signalling. The LED pin is a full push-pull CMOS
driver.
K2L Key-To-LED Function: This bit (one per key) enables
the associated key, when active, to force the LED pin active
for one and only one complete burst cycle (during all 10 keys
starting from timeslot 0); this is a one-shot output. If there is
also an ongoing major error, the major error takes
precedence and LED stays solid-active. The 10 µs Heartbeat
pulse (see below) still exists after timeslot 9. It is possible to
have multiple keys’ K2L bits enabled. K2L can be used to
establish a redundant signalling path for important ‘Halt’ or
‘Panic’ keys etc. The KEYO function is overridden by K2L for
one scan cycle.
K2L in Standalone Mode: K2L is automatically enabled on
all keys in standalone mode when no EEPROM is present.
This can be used to interrupt a host controller whenever any
enabled key is touched.
Heartbeat Pulses: At the end of each complete keyscan
after the timeslot for key 9, the LED pin will pulse low for
10µs as a ‘health’ indicator. The exception to this is if the
LEDP control bit is high (active high LED drive), in which
case Heartbeat pulses are disabled. It is possible to monitor
the Heartbeat pulse in a way that confirms the device is
operating properly.
LEDP LED Polarity Function Control Bit. This bit controls
the active polarity of the LED output. If it is 0, the LED pin is
active low (default state). If LEDP = 1, the output is active
high. In addition, with LEDP = 1, heartbeat signals are not
present on the LED line.
KEYO Key Output Control Bit: This bit causes the LED to
pulse active if there are keys in detection, during the timeslot
of the active key.
In addition to the heartbeat pulse after timeslot 9, the LED
pin will pulse active during the burst of the active key’s
timeslot. For example; if key 3 is active, there will be an
active KEYO pulse during the next occurrence of timeslot 3.
The pulse will be as wide as the timeslot. The KEYO function
is overridden by the K2L function for one scan cycle. The
KEYO function affects all keys.
Major errors: Any major error (those not involving disabled
keys) will cause the LED pin to become solid-active. A major
error is one where an enabled key signal falls below LBLL
(Section 4.13) or rises above a value of 4095. These
conditions can happen if the Cs capacitor fails or there is a
short in the SNS circuit. A major error also includes RAM
and EEPROM CRC errors.
In Standalone Mode with no EEPROM present, keys are
disabled by strapping the SNS pins to ‘unused’ settings
(Table 1.1 page 4); this will not generate a ‘major error’
output unless the error occurs after the part has already
gone through power-up calibration successfully.
The Heartbeat ‘health’ indicator does not appear when a
‘major error’ condition exists. A ‘major error’ also overrides
the KEYO and K2L functions when detected.
For more information on error reporting see Section 2.16,
Page 14.
4.9 NDIL, FDIL - Detect Integrator Bits
NDIL: Bytes 20 - 29, Bits 3..0
FDIL: Byte 32, Bits 7..4
Default NDIL value:
2
Default FDIL value:
5
Typical values:
NDIL = 2, FDIL = 5
To suppress false detections caused by spurious events like
electrical noise, the device incorporates a 'detection
integrator' or DI counter mechanism that acts to confirm a
detection by consensus (all detections in sequence must
agree). The DI mechanism counts sequential detections of a
key that appears to be touched, after each burst for the key.
For a key to be declared touched, the DI mechanism must
count to completion without even one detection failure.
The DI mechanism uses two counters. The first is the ‘fast
DI’ counter FDIL. When a key’s signal is first noted to be
below the negative threshold, the key enters ‘fast burst’
mode. In this mode the burst is rapidly repeated for up to the
specified limit count of the fast DI counter. Each key has its
own counter and its own specified fast-DI limit (FDIL), which
can range from 1 to 15. When fast-burst is entered the
device locks onto the key and repeats the acquire burst until
the fast-DI counter reaches FDIL, or, the detection fails
beforehand. After this the device resumes normal
keyscanning and goes on to the next key.
The ‘Normal DI’ counter counts the number of times the
fast-DI counter reached its FDIL value. The Normal DI
counter can only increment once per complete scan of all
keys. Only when the Normal DI counter reaches NDIL does
the key become tagged ‘active’.
The net effect of this is that the sensor can rapidly lock onto
and confirm a detection with many confirmations, while still
LQ
27
Copyright © 2003-2005 QRG Ltd
QT1100A-ISG R3.02/1105

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