QT1106-ISG View Datasheet(PDF) - Quantum Research Group
Part Name
Description
Manufacturer
QT1106-ISG Datasheet PDF : 20 Pages
| |||
3 SPI Interface
3.1 Introduction
The QT1106 is an SPI slave mode device. This section
describes the hardware operation of this interface.
3.2 CHANGE Pin
The QT1106 has a CHANGE output pin which allows for key
state change notification. Use of the CHANGE signal
relieves the host of the burden of regularly polling the
QT1106 to get key states. CHANGE goes high when there is
a change of state, i.e. when a new key is pressed, or
released, or a movement is detected on the wheel/slider.
CHANGE also goes high after a reset to indicate to the host
that it should do an SPI transfer in order to provide initial
configuration information to the QT110 6 (as it does on every
SPI transfer).
CHANGE goes low after the status is read through an SPI
transfer.
3.3 SPI Parameters
The SPI transmission parameters are:
# 70kHz max clock rate
# 8 data bits
# 6.7µs min low clock period
# 6.7µs min high clock period
# Three bytes per transmission, byte 1 most significant bit
sent first
# Clock idle high
# Shift out on falling edge
# Shift in on rising edge
The host must always transfer three bytes in succession
within the allotted time (10ms maximum). If all bytes are not
received in this interval it is treated by the QT1106 as an
error and the DRDY line will go low before the transmission
is completed.
Messages from the host to the QT110 6 carry configuration
information; return data from the QT1106 carries key state
information. For details of the message contents see
Sections 3.5 and 3.6.
3.4 SPI Operation
The basic timing diagram for SPI operation is shown in
Figure 3.1 The host does the clocking and controls the
timing of the transfers, subject to Data Ready (DRDY), from
the QT1106. Transfers are always clocked as a set of three
bytes, Byte 1, 2 and 3.
The host should not attempt to clock the SPI bus to the
device while DRDY is low; during DRDY low the QT1106 is
busy and will ignore SPI activity, with the exception of a 20µs
grace period after the fall of DRDY, where there are no
communications during the high period of DRDY .
DRDY stays high for at least 450µs. It falls again after Byte 3
has shifted to indicate completion. After the fall of DRDY, the
device acquires (bursts). DRDY goes high to permit SPI
activity after each burst.
After the host asserts /SS low, it should wait > 22µs before
starting SCLK. The QT1106 reads the MOSI pin with each
rising edge of SCLK, and shifts data out on the MISO pin on
falling edges. The host should do the same to ensure proper
operation.
Between the end of the Byte 1 shift and the start of the
Byte 2 shift (and between Byte 2 and Byte 3), the host may
raise /SS again, but this is not required; the QT1106 ignores
/SS during transfer of the three bytes.
All timings not mentioned above should be as in Figure 3.1.
/SS Wake Operation: /SS is also used to wake the device
from sleep, see Section 4.3
Figure 3.1 SPI Operation
Acquire Bursts
DRDY from QT
/SS from host
<470us
>22us
<10ms
/SS may go high between
bytes; QT1106 ignores this
>6.7us
>6.7us
SCLK from Host
Data sampled on rising edge
Data shifts out on falling
Host Data Output
(QT1106 Input - MOSI)
don't care
76543210
Command Byte 1
QT Data Output
(QT1106 Out - MISO)
Response Byte 1
3-state ? 7 6 5 4 3 2 1 0
<17us
/SS pulse during 25us grace period
>450us
don't care
76543210
Command Byte 2
Response Byte 2
76543210
DRDY from QT
<20us
(grace period)
/SS from host
/SS may go high
between bytes;
QT1106 ignores this
>0us
>10.8us
>0us
don't care
76543210
Command Byte 3
Response Byte 3
76543210
~23ms
240ms
<5.7us
don't care
don't care
>0ns <500ns
3-state
Lq
8
QT1106-ISG R8I.05/0906
Share Link: 