QT60326 View Datasheet(PDF) - Quantum Research Group
Part Name
Description
Manufacturer
QT60326 Datasheet PDF : 32 Pages
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Multi-drop capability: Tx floats within 10µs after each
transmitted byte. This line can thus be shared with other UART
based peripherals. Tx includes an internal 20K ~ 50K pull-up
resistor to Vdd to prevent the line from floating down.
Wake operation: The device can be put into sleep mode with a
serial command, 0x16 (page 16) and then be awaked with a
dummy byte from the host, if the Rx and WS pins are connected
together. The first received UART byte from the host after a
wake should be a 0xFF; any other byte value could create a
framing error. The start bit of the 0xFF forms a convenient
narrow wake pulse without being long enough to be interpreted
as a byte during the wake operation.
The recommended method to reestablish communications after
Wake from Sleep is to send a 0x0F ('Get Last Command'
command) repeatedly until the correct response comes back
(the command's own compliment, i.e. 0xF0).
Rx - Receive async data. This pin is an input only.
Tx - Transmit async data. Drives out when transmitting but
floats within 10µs of the end of the stop bit, to allow bussing
with several similar parts. Tx should idle high, and it includes
an internal 20K ~ 50K resistor to Vdd. Tx is push-pull when
transmitting data for good drive characteristics.
UART transmission parameters are:
Baud rate:
9600 ~ 115,200
Start bits:
1
Data bits:
8
Parity:
None
Stop bits:
1
DRDY in UART mode: Section 3.1 applies.
DRDY is bi-directional in UART mode. DRDY can be pulled
down by either the QT or the host (wire-AND), so that either
device can be inhibited from sending data until the other is
ready. The host should obey this control line or transmission
errors can occur. The host should grant a 10µs grace period
after clamping DRDY low in which it can still accept the start bit
of a transmission from the QT.
As explained in Section 3.1, DRDY is not clamped low
immediately after the QT receives a byte; there can be up to a
20µs delay from the end of the stop bit before DRDY goes low.
Sampling of DRDY by the host should occur 20µs after the byte
has been fully sent; if DRDY is already high at this point, or
becomes high, then it is clear to send.
Null Bytes: Unlike SPI mode, there is no reason to send null
bytes to the QT in UART mode. The QT device will respond to
commands with data when ready, subject to the DRDY line
being high.
UART Noise: In some designs it is necessary to run Tx and Rx
over a lengthy distance. This can introduce ringing, ground
bounce, and other noise problems which can corrupt data.
Figure 3-4 UART Timing
Figure 3-5 UART Connections
Host MCU
QT60xx6
Rx
Tx
P_IN
Tx
Rx
DRDY
Simple RC networks and slower data rates are helpful to
resolve these issues. CRC checks have been added to critical
commands in order to detect transmission errors to a high level
of certainty.
UART Timing Parameters: UART timings are as shown in
Figure 3-4. Delay timings for parameters U2 and U3 are
dependent on the specific command. See Section 4.
4 Control Commands
Refer to Table 4.2, page 18 for further details.
Suggested command sequencing: See Section 4.23, page 16.
The devices feature a set of commands which are used for
control and status reporting. The host device has to send the
command to the QT60xx6 and await a response.
SPI mode: While waiting the host should delay for 20 µs from
the end of the command, then start to check if DRDY is or goes
high. If it is high, then the host master can clock out the
resulting byte(s).
UART mode: After the command is sent, the QT will send back
the response usually starting within 1ms. The host can clamp
DRDY low (wire-AND logic) to inhibit a response if the host is
not able to receive the transmission for a while.
Command timeouts: Where a command involves multi-byte
transfers in either direction, each byte must be transmitted
within 100ms of the prior byte or the command will timeout. No
error is reported for this condition; the command simply ceases.
Word return byte order: Where a word or long word is
returned (16 or 24 bit number or bit pattern) the low order byte
is sent or received first.
Response delays: The device requires processing time to
complete command requests and respond with an answer to
the host. These timings are the same for SPI and UART modes.
Most commands respond with data in 1ms maximum; timing
parameters U2 and U3 in Figure 3-4 will thus be 1ms maximum
for these commands. The exceptions are:
0x01 (Setups upload):
0x0E (Get eeprom CRC):
0x16 (Sleep):
<5ms
<20ms
<20ms
DRDY (handshake)
Rx (command from host)
*
Tx (response to host)
floats high
U1
U1: <=20us U2, U3: See text; U4: <10us
U3
U2
*
* Stop bit
floats high
U4
4.1 Null Command - 0x00
Used to shift back data from the QT in SPI
mode. Since the host device is always the
master in SPI mode, and data is clocked in
both directions, the Null command is
required frequently to act as a placeholder
where the desire is to only get data back
from the QT, not to send a command.
lQ
13
QT60486-AS R8.01/0105
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