R2A20124AFP-U0 View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
R2A20124AFP-U0 Datasheet PDF : 13 Pages
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R2A20124AFP/R2A20124ASP
Preliminary
Electrical Characteristics (cont.)
(Ta = 25°C, Vcc = 12 V, RT = 180 k, Rdelay = 51 k, Rramp-slp = 27 k, unless otherwise specified.)
Item
Symbol
Min
Typ
Max Unit
Test Conditions
PHASE MODULATOR: R2A20124AFP/ASP
RAMP offset voltage
RAMP source current
RAMP sink current
Minimum phase shift
Maximum phase shift
Delay to OUT-C, -D *2
RAMP discharge time *1
VRAMP
Isource-RAMP
ISINK-RAMP
Dmin
Dmax
Tpd
Tdis
1.035
–220
3
—
—
—
—
1.135
–185
10
0*1*4
97.0*1*4
100
80
1.235
–150
—
—
—
200
120
V
A RAMP = 0.15 V, COMP; open
mA RAMP = 0.15 V, COMP = 0 V
% RAMP = 0 V, COMP = 0 V
% RAMP = 0 V, COMP = 2.1 V
ns COMP = 1.6 V
ns FB(–) = 0.75 V, COMP; open
RAMP-SLP voltage
DELAY: R2A20124AFP/ASP
DELAY-1, -2 *3
DELAY-3 *3
DELAY2-1, -2 *1*3
DELAY2-3 *1*3
Terminal voltage
SOFT START: R2A20124AFP/ASP
VRAMP-SLP
TD1, 2
TD3
TD2_1, _2
TD2_3
VD1, 2, 3
2.1
2.3
2.5
V
70
100
130
ns Delay set R = 51 k
45
65
85
ns Delay set R = 51 k
140
220
300
ns Delay set R = 180 k
110
170
230
ns Delay set R = 180 k
1.9
2.0
2.1
V
Delay set R = 51 k
Source current
ISS
–14
–10
–6
A SS = 1 V
SS high voltage
VOH-SS
3.9
4.0
4.1
V
Notes: 1. Design specification (reference data)
2. Tpd is defined as;
RAMP
1V
0V
50%
OUT-C/D
VCC
0V
50%
Tpd
3. TD1, TD2, and TD3 are defined as;
TD1
TD1
OUT-A
For primary
OUT-B
50%
control
OUT-C
OUT-D
TD2
TD2
OUT-E
For secondary
control
TD3
OUT-F
4. Maximum/Minimum phase shift is defined as;
D
=
T2
T1
×
2
×
100
(%)
OUT-A
T2
OUT-D
OUT-B
OUT-C
T1
TD3
T2
T1
R03DS0031EJ0300 Rev.3.00
Mar 11, 2011
Page 9 of 12
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