R8830 View Datasheet(PDF) - RDC Semiconductor
Part Name
Description
Manufacturer
R8830 Datasheet PDF : 97 Pages
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RDC®
RISC DSP Controller
63
PCS2 / CTS1/ ENRX1
4
RFSH2 / ADEN
5
WR
6
RD
7
ALE
8
ARDY
9
S2
10
S1
11
S0
R8830
Clear to Send/Enable Receiver Request signal for
asynchronous serial port 0. when ENRX 1 bit in the
AUXCON register is cleared and the FC bit in the serial port
Output/Input
0 control register is set the CTS1signal is enabled. otherwise
when ENRX 1 bit is set and the FC bit is set the ENRX 1
signal is enabled.
Bus Interface
For RFSH2 feature, this pin actice low to indicate a DRAM
refresh bus cycle.
For ADEN feature, when this pin is held high on power-on
reset the address portion of the AD bus can be disabled or
enabled by DA bit in the LMCS and UMCS register during
Output/Input LCS or UCS bus cycle access. The RFSH2 / ADEN with a
internal weak pull-up resister, so no external pull-up resister is
reqired. The AD bus always drives both address and data
during LCS or UCS bus cycle access, if the
RFSH2 / ADEN pin with external pull-Low resister during
reset.
Write strobe. This pin indicates that the data on the bus is to be
Output
Output
Output
Input
written into a memory or an I/O device. WR is active during
T2, T3 and Tw of any write cycle, floats during a bus hold or
reset.
Read Strobe. Active low signal which indicates that the
microcontroller is performing a memory or I/O read cycle.
RD floats during bus hold or reset.
Address latch enable. Active high. This pin indicates that an
address output on the AD bus. Address is guaranteed to be
valid on the trailing edge of ALE. This pin is tri-stated during
ONCE mode and is never floating during a bus hold or reset.
Asynchronous ready. This pin performs the microcontroller
that the address memory space or I/O device will complete a
data transfer. The ARDY pin accepts a rising edge that is
asynchronous to CLKOUTA and is active high. The falling
edge of ARDY must be synchronized to CLKOUTA. Tie
ARDY high, the microcontroller is always asserted in the ready
condition. If the ARDY is not used, tie this pin low to yield
control to SRDY.
Bus cycle status. These pins are encoded to indicate the bus
status. S2 can be used as memory or I/O indicator. S1 can be
Output
used as DT/ R indicator. These pins are floating during hold
and reset.
Bus Cycle Encoding Description
S2 S1 S0
Bus Cycle
0 0 0 Interrupt acknowledge
0 0 1 Read data from I/O
0 1 0 Write data to I/O
0 1 1 Halt
1 0 0 Instruction fetch
1 0 1 Read data from memory
1 1 0 Write data to memory
1 1 1 Passive
RDC Semiconductor Co.
Subject to change without notice
9
Rev:1.4
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