R8830I View Datasheet(PDF) - RDC Semiconductor
Part Name
Description
Manufacturer
R8830I Datasheet PDF : 5 Pages
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RDC®
RISC DSP Communication
1. Features
R8830I
16-BIT RISC MICROCONTROLLER
l CPU Core
- RDC’s proprietary RISC architecture
- Five-stage pipeline
- CPU Clock speed: 20/25/33 MHz
- Supports CPU ID
- Supports 32 PIO pins
l Bus interface
- Multiplexed address and data bus which is
compatible with the 80C188 microprocessor
- Supports a non-multiplexed address bus A[19:0]
l ROM/RAM Controller and Addressing Space
- 1M-byte memory address space
- 64K-byte I/O space
l PSRAM Interface
- PSRAM (Pseudo Static RAM) interface with
auto-refresh control
l Compatible UART Channels
- UART speed : maximum baud rate up to
115.2Kbps
l Two Independent DMA Channels
- Supports serial ports with DMA transfers
l Asynchronous Serial Channels
- Supports two asynchronous serial channels
with hardware handshaking signals
l Interrupt Controller
- The Interrupt controller with seven maskable
external interrupts and one non-maskable
external interrupt
l Programmable Chip-select Logic
- Programmable chip-select logic for memory or
I/O bus cycle decoder
l Programmable Wait-state Generator
l Counter/Timers
- Three independent 16-bit timers and one
independent watchdog timer
l Software Compatible with the 80C186
Microprocessor
l Operating Voltage Range
- Core voltage: 5V ± 10%
- I/O voltage: 5V ± 10%
l Ambient temperature: - 40 ~ +85°C
l Power Save and Power Down Mode Support
l Package Type
-100 Pin PQFP & 100 Pin LQFP
Specifications subject to change without notice, contact your sales representatives for the most update information.
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REV 1.0 Mar. 23 2007
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