R8A66174SP View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
R8A66174SP Datasheet PDF : 12 Pages
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R8A66174SP
BLOCK DIAGRAM
DATA BUS
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
COMMAND/
DATA INPUT
CHIP SELECT
INPUT
WRITE INPUT
C/D 19
CS 18
WR 1
CLOCK INPUT
INTERRUPT
REQUEST
OUTPUT
Φ 11
INT 16
RESET
INPUT
RESET 17
8
SELECTOR
WR
63 X 8-BIT
SRAM
DECODER
LOAD
CK
8-BIT
SHIFT
REGISTER
SELECTOR
S
INPUT
CONTROL
CIRCUIT
WRITE
COUNTER
CK
RD
CK
COMMAND REGISTER
DIVIDER
F/F GATE
READ
COUNTER CK
RD
BIT/BYTE
CONVERTER
MATCHING
DETECTION
CIRCUIT
13 SDATA SHIFT DATA
OUTPUT
SHIFT CLOCK
12 SCLK OUTPUT
14 LATCH LATCH OUTPUT
15 OE
OUTPUT ENABLE
OUTPUT
FUNCTIONAL DESCRIPTION
The information on data bus D0~D7 is loaded as command when C//D=1, and as data when C//D=0.
There are four kinds of commands.
(1) Command 1. Five kinds of division ratios of the clock input are set up.
(2) Command 2. R8A66174 is set as write mode. The CPU is capable of writing 8-bit parallel data of up to 63
bytes into the internal memory (FIFO) of the R8A66174.
(3) Command 3. R8A66174 is set as serial output mode. All data written in the internal memory (FIFO) is
outputted as serial data in sync with the shift clock which is set by command 1. Then, each data is
outputted from LSB. When all stored data has outputted, R8A66174 will output the interrupt request /INT
to CPU.
(4) Command 4. cancels the /INT and sets/resets the two control ports (LATCH, /OE).
After command4, if command3 is executed immediately, the data which is already written will be re-outpu-
tted.
FUNCTION TABLE
Input
Outputs
Control inputs
Data inputs
SCLK SDATA /INT /OE LATCH
/R /CS C//D /WR D7 D6 D5 D4 D3 D2 D1 D0
Remark
－ 0 × × × × × × × × × × × 0 0 1 1 0 Initialize
－ 1 1 × × × × × × × × × × * 1 * 1 * 1 * 2 * 2 Memory contents not changed
101
1000××××001
Φ
1001
001
1/2 division of Φ
Valid when D7 is
1
1010
001
1/4 division of Φ
high-level
1011
001
1/8 division of Φ
1100
001
1/16 division of Φ
1
0×××0××0001
WRITE MODE setting
2
WRITE MODE
0
××××××××001
WRITE operation
1
0 × × × 0 × × 1 *3 *4 1
3
*5 × × × × × × × × × × *3 *4 1
*5 × × × × × × × × × × 0 0 0
SERIAL OUT MODE setting
SERIAL OUT
SERIAL OUT end
SERI. OUT
MODE
4
01
0 × × × 1 D2 D1 × 0 0 1 D2 D1 set/reset the /OE and LATCH, cancel /INT
Note1 *1 : The same operation as *3 and *4 in the SERIAL OUT mode. The output is not changed in other modes.
*2 : The output is not changed.
*3 : The Φ division pulse which is set by command 1 is outputted on /WR rise.
*4 : SDATA (n) is output on SCLK fall (n-1).
*5 : Indicates 1 when /WR is 0, don't care when /WR is 1.
X : Don't care
REJ03F0278-0101 Rev.1.01 Oct.06.2008
Page 2 of 11
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