R8A66174SP View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

R8A66174SP

PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO

Renesas Electronics 

R8A66174SP

TIMING DIAGRAM

Instruction set 1~4

Φ

(Note 13)

tc(Φ)

tw(Φ)

Note 14 : Output when command 3 is set.

Note 15 : Output when command 4 is set.

C/D, CS

INPUTS

WR

D0~D7

SCLK

(Note 14)

OUTPUTS

SDATA

(Note 14)

OE, LATCH

(Note 15)

INT

(Note 15)

tsu(A-/W)

tw(/W)

tsu(D-/W)

th(/W-A)

th(/W-D)

tPLH(/W-SC)

tPLH(/W-/OE), (/W-LA)

tPHL(/W-/OE), (/W-LA)

First byte

LSB

tPLH(Φ-SC)

tPLH(Φ-SD)

tPHL(Φ-SD)

Last byte

MSB

trec(/INT-/W)

tPLH(/W-/INT)

Note 13 : The timing diagram when division ratio is set (1/2, 1/4, 1/8, 1/16) is regarded as the waveform as divided by Φ.

There are specific Φ inputs for switching from each Φ state.

tPHL(Φ-/INT)

Timing diagram when RESET

INPUTS

RESET

WR

OE

OUTPUTS LATCH

INT

tw(/R)

trec(/R-/W)

tPLH(/R-/OE)

tPHL(/R-LA)

tPLH(/R-/INT)

WR recovery time other than data reading

INPUT

WR

trec(/W)

REJ03F0278-0101 Rev.1.01 Oct.06.2008

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