RM5261 View Datasheet(PDF) - PMC-Sierra

Part Name

Description

Manufacturer

RM5261

Microprocessor with 64-Bit System Bus

PMC-Sierra 

RM5261™ Microprocessor with 64-Bit System Bus Data Sheet

Released

unit and a pipelined multiply/add unit. Overlap of the divide/square root and multiply/add

operations is supported.

The RM5261 maintains fully precise floating-point exceptions while allowing both overlapped

and pipelined operations. Precise exceptions are extremely important in object-oriented

programming environments and highly desirable for debugging in any environment.

Floating-point operations include:

• add

• subtract

• multiply

• divide

• square root

• reciprocal

• reciprocal square root

• conditional moves

• conversion between fixed-point and floating-point format

• conversion between floating-point formats

• floating-point compare.

Table 2 gives the latencies of the floating-point instructions in internal processor cycles.

Table 2 Floating-Point Instruction Cycles

Operation

Latency

fadd

4

fsub

4

fmult

4/5

fmadd

4/5

fmsub

4/5

fdiv

21/36

fsqrt

21/36

frecip

21/36

frsqrt

38/68

fcvt.s.d

4

fcvt.s.w

6

fcvt.s.l

6

fcvt.d.s

4

fcvt.d.w

4

fcvt.d.l

4

fcvt.w.s

4

fcvt.w.d

4

fcvt.l.s

4

Repeat Rate

1

1

1/2

1/2

1/2

19/34

19/34

19/34

36/66

1

3

3

1

1

1

1

1

1

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

14

Document ID: PMC-2002241, Issue 1

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