RM5261™ Microprocessor with 64-Bit System Bus Data Sheet
Released
List of Figures
Figure 1 Block Diagram .............................................................................................................10
Figure 2 CPU Registers .............................................................................................................11
Figure 3 Pipeline ........................................................................................................................12
Figure 4 CP0 Registers .............................................................................................................16
Figure 5 Kernel Mode Virtual Addressing (32-bit) .....................................................................17
Figure 6 Typical Embedded System Block Diagram .................................................................21
Figure 7 Processor Block Read .................................................................................................23
Figure 8 Processor Block Write .................................................................................................23
Figure 9 Clock Timing ................................................................................................................35
Figure 10 Input Timing ...............................................................................................................35
Figure 11 Output Timing ............................................................................................................35
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
7
Document ID: PMC-2002241, Issue 1