S25FL127S View Datasheet(PDF) - Spansion Inc.
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S25FL127S Datasheet PDF : 131 Pages
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Data Sheet (Preliminary)
4.3.9
Single Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash
memory array before transfer to the host. The number of latency cycles are determined by the Latency Code
in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low, and
HOLD# high. The Write Protect (WP#) signal is ignored. The host may drive the SI signal during these cycles
or the host may leave SI floating. The memory does not use any data driven on SI / I/O0 or other I/O signals
during the latency cycles. In dual or quad read commands, the host must stop driving the I/O signals on the
falling edge at the end of the last latency cycle. It is recommended that the host stop driving I/O signals during
latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive
at the end of the latency cycles. This prevents driver conflict between host and memory when the signal
direction changes. The memory does not drive the Serial Output (SO) or I/O signals during the latency cycles.
The next interface state depends on the command structure i.e. the number of latency cycles, and whether
the read is single, dual, or quad width.
4.3.10
Single Output Cycle - Memory to Host Transfer
Several commands transfer information back to the host on the single Serial Output (SO) signal. The host
keeps RESET# high, CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The memory
ignores the Serial Input (SI) signal. The memory drives SO with data.
The next interface state continues to be Single Output Cycle until the host returns CS# to high ending the
command.
4.3.11
Dual Input Cycle - Host to Memory Transfer
The Read Dual I/O command transfers two address or mode bits to the memory in each cycle. The host
keeps RESET# high, CS# low, HOLD# high. The Write Protect (WP#) signal is ignored. The host drives
address on SI / IO0 and SO / IO1.
The next interface state following the delivery of address and mode bits is a Dual Latency Cycle if there are
latency cycles needed or Dual Output Cycle if no latency is required.
4.3.12
Dual Latency (Dummy) Cycle
Read commands may have zero to several latency cycles during which read data is read from the main flash
memory array before transfer to the host. The number of latency cycles are determined by the Latency Code
in the configuration register (CR[7:6]). During the latency cycles, the host keeps RESET# high, CS# low, and
HOLD# high. The Write Protect (WP#) signal is ignored. The host may drive the SI / IO0 and SO / IO1 signals
during these cycles or the host may leave SI / IO0 and SO / IO1 floating. The memory does not use any data
driven on SI / IO0 and SO / IO1 during the latency cycles. The host must stop driving SI / IO0 and SO / IO1
on the falling edge at the end of the last latency cycle. It is recommended that the host stop driving them
during all latency cycles so that there is sufficient time for the host drivers to turn off before the memory
begins to drive at the end of the latency cycles. This prevents driver conflict between host and memory when
the signal direction changes. The memory does not drive the SI / IO0 and SO / IO1 signals during the latency
cycles.
The next interface state following the last latency cycle is a Dual Output Cycle.
4.3.13
Dual Output Cycle - Memory to Host Transfer
The Read Dual Output and Read Dual I/O return data to the host two bits in each cycle. The host keeps
RESET# high, CS# low, and HOLD# high. The Write Protect (WP#) signal is ignored. The memory drives
data on the SI / IO0 and SO / IO1 signals during the dual output cycles.
The next interface state continues to be Dual Output Cycle until the host returns CS# to high ending the
command.
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S25FL127S
S25FL127S_00_02 April 25, 2013
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