FL208KIF View Datasheet(PDF) - Spansion Inc.
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FL208KIF Datasheet PDF : 37 Pages
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Data Sheet (Preliminary)
Figure 8.8 Page Program Command Sequence
CS#
Mode3 0 1 2 3 4 5 6 7 8 9 10
SC K M ode0
28 29 30 31 32 33 34 35 36 37 38 39
Instruction (02H )
24-Bit Address
Data Byte 1
SI/IO0
23 22 21
*
3 2 1 07 6 5 4 3 2 1 0
*
SO
High Im pedance
CS#
SC K
SI/IO0
SO
*=M SB
40 41 41 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
7 6 5 4 3 2 10 7 6 5 4 32 1 0
*
*
High Im pedance
Mode3
Mode0
Data Byte 256
7 6 5 4 3 2 10
*
8.9
Sector Erase (SE) (20h)
The Sector Erase command sets all bits in the addressed 4 kB sector to 1 (all bytes are FFh). Before the
Sector Erase command can be accepted by the device, a Write Enable command must be issued and
decoded by the device, which sets the Write Enable Latch bit in the Status Register to enable any write
operations. The command is initiated by driving the CS# pin low and shifting the command code “20h”
followed by a 24-bit sector address (A23-A0). The Sector Erase command sequence is shown in Figure 8.9.
The CS# pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase command will not be executed. After CS# is driven high, the self-timed Sector Erase command
will commence for a time duration of tSE. See AC Characteristics on page 31. While the Sector Erase cycle is
in progress, the Read Status Register command may still be accessed for checking the status of the WIP bit.
The WIP bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device
is ready to accept other commands again. After the Sector Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Sector Erase command will not be executed if the
addressed page is protected by the Block Protect (BP3, BP2, BP1, and BP0) bits (see Table 7.1 on page 13).
August 14, 2012 S25FL208K_00_05
S25FL208K
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