S3C72K8 View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
S3C72K8 Datasheet PDF : 30 Pages
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S3C72K8/P72K8
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C72K8 Pin Descriptions
Pin Name Pin
Type
Description
P0.0
P0.1
P0.2
P0.3
I/O 4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
Individual pins are software configurable as open-
drain or push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P1.0
P1.1
P1.2
P1.3
I 4-bit input port.
1-bit or 4-bit read and test are possible.
The 1-bit unit pull-up resistors are assigned to input
pins by software.
An interrupt is generated by digital input at P1.0,
P1.1.
P2.0–P2.3 I/O Same as port 0 except that 8-bit read/write and test is
possible.
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
I/O Same as port 0 except that port 4 is 3-bit I/O port.
P5.0–P5.7 O Output port for 1-bit data
Circuit
Type
E–2
F–4
F–4
A–3
A–3
E–2
E–2
H–11
SCK
I/O Serial I/O interface clock signal
E–2
SO
I/O Serial data output
E–2
SI
I/O Serial data input
E–2
BUZ
I/O 2 KHz, 4 KHz, 8 KHz or 16 KHz frequency output at
E–2
the watch timer clock frequency of 32.768 kHz.
K0–K3 I/O External interrupt. The triggering edge is selectable.
E–2
INT0
INT1
I External interrupts. The triggering edge for INT0 and
F–4
INT1 is selectable.
INT2
I Quasi-interrupt with detection of rising or falling
A–3
edges
INT4
I External interrupts with detection of rising and falling
A–3
edges
Pin
Number
8
9
10
11
Share Pin
K0/SCK
K1/SO
K2/SI
K3/BUZ
20 INT0/CIN0
21 INT1/CIN1
22
INT2
23
INT4
24–27
–
28
29
30
31
32
33
34
75–
80,1,2
8
9
10
11
–
–
LCDSY
LCDCK
CLO
TCL0
TCLO0
SEG32–
SEG39
P0.0/K0
P0.1/K1
P0.2/K2
P0.3/K3
8–11
20
21
22
P0.0–P0.3
P1.0/CIN0
P1.1/CIN1
P1.2
23
P1.3
1-5
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