S5L9284 View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

S5L9284

DIGITAL SIGNAL PROCESSOR

Samsung 

DIGITAL SIGNAL PROCESSOR

S5L9284D

PIN DESCRIPTION (Continued)

Pin No.

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

Symbol

SBCK

SBDT

DVDD1

MUTE

MLT

MDAT

MCK

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

FLAG1

FLAG2

FLAG3

FLAG4

FLAG5

52

/PBCK

53

DVSS2

54

FSDW

55

ULKFS

56

/JIT

57

C4M

58

C16M

59

/WE

60

/ CS

61

SEL1

62

SEL2

I/O

Description

I Subcode data bit clock

O Subcode serial data output

− Digital supply voltage 1

I Mute control input (“H”: Mute ON)

I Latch signal input from micom

I Serial data input from micom

I Serial data transferring clock input from micom

I/O Data port 7 for external SRAM (MSB)

I/O Data port 6 for external SRAM

I/O Data port 5 for external SRAM

I/O Data port 4 for external SRAM

I/O Data port 3 for external SRAM

I/O Data port 2 for external SRAM

I/O Data port 1 for external SRAM

I/O Data port 0 for external SRAM (LSB)

I/O Monitoring output for C1 error correction (RA0)

I/O Monitoring output for C1 error correction (RA1)

I/O Monitoring output for C2 error correction (RA2)

I/O Monitoring output for C2 error correction (RA3)

I/O C2 decoder flag (“H”: when the processing C2 code is in impossible correction

status /RA4)

I/O VCOI/2 clock (4.3218/8.6436 MHz), when locked in with EFMI (RA5)

− Digital ground 2

I/O Unprotected frame sync (RA6)

I/O Frame sync protection status (RA7)

I/O RAM overflow and underflow status (RA8)

I/O 4.2336 MHz clock output (RA9)

I/O 16.9344 MHz clock output (RA10)

I/O Write enable output to external SRAM

I/O Chip select output to external SRAM

I X-tal selection terminal (“L”:16.9344 MHz, “H”: 33.8688 MHz)

I DPLL selection terminal (“L”: DPLL, “H”: APLL)

5

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