S5L9291X01-T0R0 View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

S5L9291X01-T0R0

DIGITAL SIGNAL PROCESSOR

Samsung 

DIGITAL SIGNAL PROCESSOR

S5L9291X

$98 Command (Default Values D [7:0] = 0000 0111)

Control cycle and gain control in CLV speed mode

Command Address

Data

D7

D6

D5

D4

D3

D2

D1

CLV gain 10011000 OVSPL WBN WPN LOCK OVSPL WB

WP

control

($98)

HIGH

MS

OVSPL (option)

Over sampling of CLV output (SMDP, SMDS) cycle by 7.35kHz * 4 and output.

H : Over-sampling Enable

L : Over-sampling Disable

WBN (option)

CLV speed mode Bottom Hold cycle control

H : RFCK/64

L : determined by WB

WPN (option)

CLV speed mode Peak Hold cycle control

H : RFCK/8

L : determined by WP

LOCK_HIGH

LOCK PAD as 'H' while Command is input.

H : LOCK High

L : Normal Lock

OVSPL_MS (option)

Over-sampling Enable SMDS Output Mode Select

H : PWM (H, L)

L : Tri-State (H, Hi-Z, L)

WB

CLV speed mode Bottom Hold Cycle Control

H : RFCK/16

L : RFCK/32

WP

CLV speed mode Peak Hold Cycle Control

H : RFCK/2

L : RFCK/4

{WPN,WP}

00

01

10

11

Control Cycle

RFCK/4

RFCK/2

RFCK/8

1RFCK/8

{WBN,WB}

00

01

10

11

Control Cycle

RFCK/32

RFCK/16

RFCK/64

RFCK/64

GAIN

CLV speed mode SMDS Output GAIN Control

H : 0dB

L : -12dB

D0

GAIN

31

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