S5L9291X01-T0R0 View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
S5L9291X01-T0R0 Datasheet PDF : 88 Pages
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S5L9291X
DIGITAL SIGNAL PROCESSOR
PIN DESCRIPTION (Continued)
Pin No
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
Symbol
D8
CLK
AD12
AD11
AD9
AD8
AD7
AD6
AD5
AD4
AD3
VSSD4
VDDD5
AD2
AD1
AD0
AD10
BA1(CS1)
BA0
CS0
RAS
CAS
90
WE
91
VSSD5
92
VDDD6
93
D7
94
D6
95
D5
96
D4
97
D3
98
D2
99
D1
100
D0
I/O
Description
I/O
DRAM data input/output 8 (3-State Output)
O
SDRAM Clock(4MHz) (3-State Output
O
DRAM address output 12 (3-state output)
O
DRAM address output 11 (3-state output)
O
DRAM address output 9 (3-state output)
O
DRAM address output 8 (3-state output)
O
DRAM address output 7 (3-state output)
O
DRAM address output 6 (3-state output)
O
DRAM address output 5 (3-state output)
O
DRAM address output 4 (3-state output)
O
DRAM address output 3 (3-state output)
-
Digital Ground
-
Digital Power
O
DRAM address output 2 (3-state output)
O
DRAM address output 1 (3-state output)
O
DRAM address output 0 (3-state output)
O
DRAM address output 10 (3-state output)
O
Bank Address 1 / DRAM Chip Select 1 (3-State Output)
O
Bank Address 0 (3-State Output)
O
DRAM Chip Select 0 (3-State Output)
O
DRAM Row Address Selection output (active Low) (3-State Output)
O
DRAM Column Address Selection output 0 (active Low) (3-State
Output)
O
DRAM Write Enable output (active Low) (3-State Output)
-
Digital Ground
-
Digital Power
I/O
DRAM data Input/Output 7 (3-State Output)
I/O
DRAM data Input/Output 6 (3-State Output)
I/O
DRAM data Input/Output 5 (3-State Output)
I/O
DRAM data Input/Output 4 (3-State Output)
I/O
DRAM data Input/Output 3 (3-State Output)
I/O
DRAM data Input/Output 2 (3-State Output)
I/O
DRAM data Input/Output 1 (3-State Output)
I/O
DRAM data Input/Output 0 (3-State Output)
6
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