S5L9286F01-Q0R0 View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

S5L9286F01-Q0R0

DIGITAL SIGNAL PROCESSOR

Samsung 

DIGITAL SIGNAL PROCESSOR FOR CDP

S5L986F01

Phase-Mode

The phase mode is the mode to control the EFM phase. Phase difference between PBFR/4 and XTFR/4 is

detected when NCLV of CNTL-Z register is "L",and phase difference between Read Base Counter/4 and Write

Base Counter/4 detected when NCLV is "H", and the difference is outputted to SMDP(Fig.14).

If the cycle of VCO/2 signal is put as "T" and it is put as "/WP" during a "H" period of PBFR, it outputs "H" to SMSD

terminal from the falling edge of PBFR to the (/WP-278T) x 32, and then, outputs "L" to the falling edge of the next

PBFR. (Figure 7)

XPHSP-Mode

The XPHSP mode is the mode used in normal operation.

The LKFS signal made from frame sync block is to sampling which period is PBFR/ 16. If the sampling is "H", the

Phase mode is performed, and if the sampling is eight of "L" continously, Speed-mode is performed automatically.

The selection of peak hold period in Speed-mode and selection of bottom hold period and gain in Speed/ Hspeed-

mode is determined by CNTL-W register.

VPHSP-Mode

The VPHSP mode is the mode used for rough servo control. It uses VCO instead of X-tal in the EFM pattern test.

When the range of VCO center changes, VCO is easily locked because the rotation of a spindle motor changes in

the same direction.

Stop-Mode

This mode stops the spindle motor.

SMDP

L

SMSD

Hi-Z

SMEF

L

SMON

L

XTFR/4;

(XTFR/8)

PBFR/4;

(PBFR/8)

SMD P

Hi-Z

Hi-Z

Hi-Z

PBFR

287T

SMSD

PBFR

288T

294T

SMSD

512T

Figure 7. SMSD, SMDP Output Timing Diagram

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