S16008MK7TW-8A View Datasheet(PDF) - Unspecified
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Description
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S16008MK7TW-8A Datasheet PDF : 9 Pages
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coincident with the READ or WRITE commands are used
to select the starting column location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, or 4 locations with burst
terminate option using the Burst Interleaved Addressing
mode only. An AUTO PRECHARGE function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 128Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while
accessing one of the other three banks will hide the
precharge cycles and provide seamless high-speed,
random-access operation.
The 128Mb SDRAM is designed to operate in 3.3V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving power-down mode.
All inputs and outputs are LVTTL-compatible. SDRAMs
offer substantial advances in DRAM operating
performance, including the abilities to synchronously
burst data at a high data rate with automatic column-
address generation, to interleave between internal banks
in order to hide precharge time, and to randomly change
column addresses on each clock cycle during a burst
access.
The x8 devices are optimized for single bank DIMM
applications. The x16 devices are available for both
single and dual bank DIMM applications.
_________________________________________
128Mb: x4, x8, x16
SDRAM 3.3V
Disclaimer:
Except as specifically provided in this document,
SpecTek makes no warranties, expressed or implied,
including, but not limited to, any implied warranties of
merchantability or fitness for a particular purpose.
Any claim against SpecTek must be made within one
year from the date of shipment from SpecTek, and
SpecTek has no liability thereafter. Any liability is limited
to replacement of the defective items or return of amounts
paid for defective items (at buyer’s election). In no event
will SpecTek be responsible for special, indirect,
consequential or incidental damages, even if SpecTek has
been advised for the possibility of such damages.
SpecTek’s liability from any cause pursuant to this
specification shall be limited to general monetary damages
in an amount not to exceed the total purchase price of the
products covered by this specification, regardless of the
form in which legal or equitable action may be brought
against SpecTek.
_________________________________
ABSOLUTE MAXIMUM RATINGS:
Voltage on Vdd Supply relative to Vss
-1 to +4.6V
Operating Temperature TA (Ambient)
Storage Temperature
25° to +70 °C
-55 to +150 °C
Power Dissipation
1W
Short Circuit Output Current
50 mA
Stresses beyond these may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at or beyond these conditions is not implied.
Exposure to these conditions for extended periods may affect
reliability.
CAPACITANCE:
Parameter
Input Capacitance: A0 - A11, BA0, BA1
Input Capacitance: RAS#, CAS#, WE#, DQM, CLK, CKE, CS#
Input/Output Capacitance: DQs
Symbol
Min
Max
CI1
1
5
CI2
1
5
CIO
1
6
Units
pF
pF
pF
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS:
Supply Voltage
Parameter
Symbol Min
Vdd/Vddq 3.0
Max
3.6
Units
V
Input High (Logic 1) Voltage, All inputs
VIH
Input Low (Logic 0) Voltage, All inputs
VIL
Input Leakage Current Any input = 0V < VIN < Vdd All other pins not under test = 0V
II
Output Leakage Current DQs are disabled; 0V < VOUT < VddQ
IOZ
Output High Voltage (IOUT = -4 mA)
VOH
Output Low Voltage (IOUT = 4 mA)
VOL
2.2 Vdd + .3
V
-0.3
0.8
V
-10
10
µA
-10
10
µA
2.4
V
0.4
V
PDF: 09005aef807827f6 / Source: 09005aef807825bd
128Mb SDRAM
Rev: 11/29/2004
2
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specifications without notice. © 2001, 2002, 2004 SpecTek
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