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SC1405D View Datasheet(PDF) - Semtech Corporation

Part Name
Description
Manufacturer
SC1405D Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
SC1405D
POWER MANAGEMENT
Pin Configuration
Top View
Ordering Information
Device
SC1405DITSTRT
Package
TSSOP-14
Temp Range (TJ)
-40° to 125°C
Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
(14-Pin TSSOP)
Pin Descriptions
Pin #
Pin Name
Pin Function
1
OVP_S
Overvoltage protection sense. External scaling resistors required to set protection
threshold.
2
EN
When high, this pin enables the internal circuitry of the device. When low, TG, BG, and
PRDY are forced low and the supply current (5V) is less than 10µA.
3
GND
Logic GND.
4
CO
TTL-level input signal to the MOSFET drivers.
5
S_MOD
When low, this signal forces BG to be low, triggering asynchronous operation. When
high, BG is not a function of this signal.
6
DELAY_C
The capacitance connected between this pin and GND sets the additional propagation
delay for BG going low to TG going high. Total propagation delay =20ns + 1ns/pF. If no
capacitor is connected, the propragation delay = 20ns.
7
PRDY
This pin indicates the status of VCC. When VCC is less than the UVLO threshold, this
output is driven low. When VCC is greater than or equals to the UVLO threshold this
output goes high.
8
VCC
Input supply of 5 - 8V. A .22-1µF ceramic capacitor should be connected from VCC to
PGND very close to the chip.
9
BG
Output drive for the synchrounous (bottom) MOSFET.
10
PGND
Power ground. Connect to the synchronous FET source pin (power ground).
11
DSPS_DR
Dynamic Set Point Switch Drive. TTL level output signal. When S-MOD is high, this pin
follows the BG driver pin voltage.
12
DRN
This pin connects to the junction of the switching and synchronous MOSFET's. This pin
can be subjected to a -2V minimum relative to PGND without affecting operation.
13
TG
Output gate drive for the switching (high-side) MOSFET.
14
BST
Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the
floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically
between 0.1µF and 1µF (ceramic).
NOTE:
(1) All logic level inputs and outputs are open collector TTL compatible.
2005 Semtech Corp.
6
www.semtech.com

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