SC1480EVB View Datasheet(PDF) - Semtech Corporation
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SC1480EVB Datasheet PDF : 22 Pages
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SC1480
POWER MANAGEMENT
Applications Information (Cont.)
Where VF is the final output voltage after release of the
load and VI is the initial voltage prior to the release of
load. If no more than 100mV of output voltage variation
is required between VF and VI , plugging in the numbers
for the application circuit yields minimum output capaci-
tance of 1000µF. As shown, a large amount of capaci-
tance is required to absorb the energy of the inductor
during a load release of 5A. In typical DDR memory appli-
cations a load release of this magnitude is not an issue
and therefore the application circuit can get by with 300µF
of output capacitance.
Stability Considerations:
Unstable operation shows up in two related but distinctly
different ways: double pulsing and fast-feedback loop
instability.
Double-pulsing occurs due to noise on the output or be-
cause the ESR is too low, causing not enough voltage
ramp in the output signal. This causes the error amplifier
to trigger prematurely after the 400ns minimum off-time
has expired. Double-pulsing will result in higher ripple
voltage at the output, but in most cases is harmless.
However, in some cases double-pulsing can indicate the
presence of loop instability, which is caused by insuffi-
cient ESR. One simple way to solve this problem is to add
some trace resistance in the high current output path. A
side effect of doing this is output voltage droop with load.
SC1480 ESR Requirements
The constant on-time control used in the SC1480
regulates the ripple voltage at the output capacitor. This
signal consists of a term generated by the output ESR of
the capacitor and a term based on the increase in voltage
across the capacitor due to charging and discharging
during the switching cycle. The minimum ESR is set to
generate the required ripple voltage for regulation. For
most applications the minimum ESR ripple voltage is
dominated by PCB layout and the properties of SP or
POSCAP type output capacitors. For applications using
ceramic output capacitors the absolute minimum ESR
must be considered. Existing literature describing the ESR
requirements to prevent double pulsing does not
accurately predict the performance of constant on-time
controllers. A time domain model of the converter was
developed to generate equations for the minimum ESR
empirically. If the ESR is low enough the ripple voltage is
dominated by the charging of the output capacitor. This
ripple voltage lags the on-time due to the LC poles and
can cause double pulsing if the phase delay exceeds the
off-time of the converter. Referring to Figure 3, the
equation for the minimum ESR as a function of output
capacitance and switching frequency and duty cycle is;
ESR
>
1
+
3
•
Fs -
200000
Fs
2• π•Cout •Fs •( 1 −D) 2
Where D = Vout/Vin. Plugging in the numbers for this
design ESR > 0.004 Ohms.
Input Capacitor Selection
Input capacitors are selected based upon the input ripple
current demand of the converter. First determine the
input ripple current expected and then choose a capacitor
to meet that demand.
The input RMS ripple current can be calculated as follows:
IRMS =
VOUT
•
(VIN
−
VOUT
)
•
IOUT
VIN
Therefore, for a maximum load current of 6.0A , the input
capacitors should be able to safely handle 3A of ripple
current. For the EVAL board, we chose two 10µF, 25V
ceramic capacitors. Each capacitor has a ripple current
capability of 2A.
MOSFET Switch Selection
The current selection of MOSFETs are determined by the
setting of the overcurrent limit circuit and the maximum
input voltage. The next step is to determine their power
handling capability. For the EVAL board the ISi4484 meet
the voltage and current requirements. This is a 30V,
10A FET. Based on 85°C ambient temperature, 150°C
junction temperature and thermal resistance, their power
handling is calculated as follows:
Power Limit for Upper & Lower FET:
T = 150°C;
J
T = 85°C;
A
θ = 50°C/W
JA
2006 Semtech Corp.
11
www.semtech.com
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