SYNCOAM Co., Ltd.
SEPS225
Version: 0.8
6) RGB Interface
When the RGB_IF register bit0 is set to “0”, SEPS225 enters into the RGB interface mode and DDRAM write
cycle is synchronized by DOTCLK.
18‐bit RGB interface
The 18‐bit RGB interface is selected by setting RIM[1:0] bits to “00”. DDRAM write operation is
Synchronized with DOTCLK and ENABLE. Display data are transmitted to DDRAM in synchronization
with 18‐bit RGB data bus(DB[17:0]) and the data enable(ENABLE).
DDRAM Write
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