SH-2A View Datasheet(PDF) - Renesas Electronics
Part Name
Description
Manufacturer
SH-2A Datasheet PDF : 501 Pages
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Item
Page
6.4.48 RTE
244
ReTurn from
Exception
System Control
Instruction
6.4.50 SETT
248
SET T bit
System Control
Instruction
6.4.57 SLEEP
257
SLEEP
System Control
Instruction
6.5.10 FLOAT
296
Floating-point
convert from integer
Floating-Point
Instruction
7.1 Overview
325
Figure 7.1 Overview
of Register Bank
Configuration
7.2.1 Banked Data 326
7.2.2 Register
326
Banks
7.2.3 Bank Control 327
Registers
(2) Bank Number
Register (IBNR) (16
bit, Initial value:
H'0000)
7.3.1 Save to Bank 328
Figure 7.2 Bank 328,
Save Operations
329
Figure 7.3 Bank
Save Timing
Revision (See Manual for Details)
Description amended
Return from
Exception Handling
Delayed Branch Instruction
Description amended
T Bit Setting
Description amended
Transition to Power-Down Mode
.
Description amended
⋅⋅⋅ When FPSCR.enable.I = 1, and FPSCR.PR = 0, an FPU
exception trap is generated regardless of whether or not an
exception has occurred.⋅⋅⋅
Figure amended
(Before) IVO → (After) VTO
Figure notes amended
VTO: Interrupt vector table address offset
Description amended
⋅⋅⋅ and the interrupt vector table address offsets (VTO) are banked.
Description amended
⋅⋅⋅ Register banks are stacked in first in last out (FILO) sequence.⋅⋅⋅
Description amended
Bits 3 to 0: BN3 to BN0
⋅⋅⋅ after which the data is retrieved from the register bank. These
bits are read-only and cannot be modified.
Description amended
(b) ..., and the interrupt vector table address offset (VTO) are
saved to the bank indicated by the BN, bank i.
Figure amended
(Before) IVN → (After) VTO
Rev. 3.00 Jul 08, 2005 page v of xiv
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