HD6437101 View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

HD6437101

32-Bit RISC Microcomputer

Renesas Electronics 

3.5 Initial State of This LSI..................................................................................................... 54

Section 4 Clock Pulse Generator ....................................................................... 55

4.1 Oscillator........................................................................................................................... 55

4.1.1 Connecting a Crystal Resonator........................................................................... 55

4.1.2 External Clock Input Method............................................................................... 56

4.2 Function for Detecting the Oscillator Halt........................................................................ 57

4.3 Usage Notes ...................................................................................................................... 57

4.3.1 Note on Crystal Resonator ................................................................................... 57

4.3.2 Notes on Board Design ........................................................................................ 57

Section 5 Exception Processing......................................................................... 59

5.1 Overview........................................................................................................................... 59

5.1.1 Types of Exception Processing and Priority ........................................................ 59

5.1.2 Exception Processing Operations......................................................................... 60

5.1.3 Exception Processing Vector Table ..................................................................... 61

5.2 Resets ................................................................................................................................ 63

5.2.1 Types of Reset ..................................................................................................... 63

5.2.2 Power-On Reset ................................................................................................... 63

5.2.3 Manual Reset ....................................................................................................... 64

5.3 Address Errors .................................................................................................................. 65

5.3.1 The Cause of Address Error Exception................................................................ 65

5.3.2 Address Error Exception Processing.................................................................... 66

5.4 Interrupts........................................................................................................................... 66

5.4.1 Interrupt Sources.................................................................................................. 66

5.4.2 Interrupt Priority Level ........................................................................................ 67

5.4.3 Interrupt Exception Processing ............................................................................ 67

5.5 Exceptions Triggered by Instructions ............................................................................... 67

5.5.1 Types of Exceptions Triggered by Instructions ................................................... 67

5.5.2 Trap Instructions .................................................................................................. 68

5.5.3 Illegal Slot Instructions ........................................................................................ 68

5.5.4 General Illegal Instructions.................................................................................. 69

5.6 Cases when Exception Sources Are Not Accepted ........................................................... 69

5.6.1 Immediately after a Delayed Branch Instruction ................................................. 69

5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 69

5.7 Stack Status after Exception Processing Ends .................................................................. 70

5.8 Usage Notes ...................................................................................................................... 71

5.8.1 Value of Stack Pointer (SP) ................................................................................. 71

5.8.2 Value of Vector Base Register (VBR) ................................................................. 71

5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 71

Rev.1.00 Sep. 18, 2008 Page x of xxxiv

REJ09B0069-0100

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