HD6437101 View Datasheet(PDF) - Renesas Electronics

Part Name

Description

Manufacturer

HD6437101

32-Bit RISC Microcomputer

Renesas Electronics 

Figure 12.2 Counter Operation .................................................................................................. 354

Figure 12.3 Count Timing ......................................................................................................... 355

Figure 12.4 CMF Set Timing..................................................................................................... 356

Figure 12.5 Timing of CMF Clear by CPU ............................................................................... 356

Figure 12.6 CMCNT Write and Compare Match Contention.................................................... 357

Figure 12.7 CMCNT Word Write and Increment Contention ................................................... 358

Figure 12.8 CMCNT Byte Write and Increment Contention..................................................... 359

Section 13 Motor Management Timer (MMT)

Figure 13.1 Block Diagram of MMT......................................................................................... 362

Figure 13.2 Sample Operating Mode Setting Procedure ........................................................... 370

Figure 13.3 Example of TCNT Count Operation ...................................................................... 371

Figure 13.4 Examples of Counter and Register Operations....................................................... 373

Figure 13.5 Example of PWM Waveform Generation .............................................................. 376

Figure 13.6 Example of TCNT Counter Clearing...................................................................... 377

Figure 13.7 Example of Toggle Output Waveform Synchronized with PWM Cycle................ 378

Figure 13.8 Count Timing ......................................................................................................... 379

Figure 13.9 TCNT Counter Clearing Timing ............................................................................ 380

Figure 13.10 TDCNT Operation Timing ..................................................................................... 380

Figure 13.11 Buffer Operation Timing........................................................................................ 381

Figure 13.12 TGI Interrupt Timing.............................................................................................. 382

Figure 13.13 Timing of Status Flag Clearing by CPU................................................................. 382

Figure 13.14 Contention between Buffer Register Write and Compare Match........................... 383

Figure 13.15 Contention between Compare Register Write and Compare Match....................... 384

Figure 13.16 Writing into Timer General Registers (When One Cycle is Not Output)............... 385

Figure 13.17 Block Diagram of POE........................................................................................... 387

Figure 13.18 Low Level Detection Operation ............................................................................. 391

Section 15 I/O Ports

Figure 15.1 Port A (SH7108)..................................................................................................... 429

Figure 15.2 Port A (SH7109)..................................................................................................... 430

Figure 15.3 Port B (SH7108)..................................................................................................... 432

Figure 15.4 Port B (SH7109)..................................................................................................... 432

Figure 15.5 Port D (SH7109)..................................................................................................... 434

Figure 15.6 Port E (SH7108) ..................................................................................................... 436

Figure 15.7 Port E (SH7109) ..................................................................................................... 437

Figure 15.8 Port F (SH7108) ..................................................................................................... 440

Figure 15.9 Port F (SH7109) ..................................................................................................... 440

Figure 15.10 Port G (SH7108)..................................................................................................... 442

Rev.1.00 Sep. 18, 2008 Page xxvii of xxxiv

REJ09B0069-0100

Share Link: