SI3000-C-GS View Datasheet(PDF) - Silicon Laboratories
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Description
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SI3000-C-GS Datasheet PDF : 34 Pages
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Si3000
Table 7. Switching Characteristics—Serial Interface
(VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 0 to 70°C, CL = 20 pF)
Parameter
Symbol Test Condition
Min
Typ
Max
Cycle Time, SCLK
tc
SCLK Duty Cycle
tdty
Delay Time, SCLK to FSYNC
td1
Delay Time, SCLK to SDO Valid
td2
Delay Time, SCLK to FSYNC
td3
Setup Time, SDI, before SCLK
tsu
Hold Time, SDI, after SCLK
th
Setup Time, FSYNC (mode 2) before
tsu
MCLK
Hold Time, FSYNC (mode 2) after
th
MCLK
354 1/256 Fs —
—
50
—
—
—
10
—
—
20
—
—
10
25
—
—
20
—
—
25
—
—
20
—
—
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V
Unit
ns
%
ns
ns
ns
ns
ns
ns
ns
SCLK
FSYNC
(mode 0)
FSYNC
(mode 1)
tc
td1
td3
VOH
VOL
td3
FSYNC
(mode 2)
16 Bit
SDO
16 Bit
SDI
High-Z
D15
D14
td2
... D2
D1
DD00
tsu
D15
th
D14 ... D2
D1
D0
Figure 2. Serial Interface Timing Diagram
High-Z
8
Rev. 1.4
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