Si3050 + Si3018/19
Table 6. Switching Characteristics—General Inputs
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C for K-Grade, CL = 20 pF)
Parameter1
Symbol
Min
Typ
Max
Unit
Cycle Time, PCLK
tp
0.12207
—
3.90625
s
PCLK Duty Cycle
tdty
40
50
60
%
PCLK Jitter Tolerance
tjitter
—
—
2
ns
Rise Time, PCLK
tr
—
—
25
ns
Fall Time, PCLK
PCLK Before RESET 2
RESET Pulse Width3
tf
—
—
25
ns
tmr
10
—
—
cycles
trl
250
—
—
ns
CS, SCLK Before RESET
tmxr
20
—
—
ns
Rise Time, Reset
tr
—
—
25
ns
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC/PCLK relationship must be fixed after RESET
3. The minimum RESET pulse width is the greater of 250 ns or 10 PCLK cycle times.
PCLK
RESET
CS, SCLK
tr
tp
tmr
trl
tmxr
Figure 2. General Inputs Timing Diagram
tf
VIH
VIL
10
Rev. 1.31